got flexpcb and pinout spec'd, fpc draft

Library.pretty/TestPoint_Bridge_Pitch2.54mm_Drill1.0mm.kicad_mod

@@ -6,7 +6,7 @@
 	(descr "wire loop as test point, pitch 2.54mm, hole diameter 1.0mm, wire diameter 0.8mm")
 	(tags "test point wire loop")
 	(property "Reference" "JP12"
-		(at -3.32 0.03 0)
+		(at 7.06 -0.01 0)
 		(layer "F.SilkS")
 		(uuid "52657ef5-2257-4914-989e-eeb5186debcb")
 		(effects
@@ -14,10 +14,11 @@
 				(size 1 1)
 				(thickness 0.15)
 			)
+			(justify left)
 		)
 	)
 	(property "Value" "~"
-		(at 5.57 -1.17 0)
+		(at 1.25 0.87 0)
 		(layer "F.Fab")
 		(uuid "93846d3d-68c5-4744-9bb3-ef5e1a747edf")
 		(effects
@@ -54,6 +55,16 @@
 		)
 	)
 	(attr through_hole exclude_from_bom)
+	(fp_line
+		(start 2.54 0)
+		(end 0 0)
+		(stroke
+			(width 0.12)
+			(type solid)
+		)
+		(layer "F.Cu")
+		(uuid "dc6cd189-aed9-4aae-ba90-97ce21a94ecb")
+	)
 	(fp_line
 		(start -1.2 -1.2)
 		(end -1.2 1.2)
@@ -134,18 +145,8 @@
 		(layer "F.CrtYd")
 		(uuid "0cc5a95c-9b7f-46ae-9521-01557d47a01c")
 	)
-	(fp_line
-		(start 2.54 0)
-		(end 0 0)
-		(stroke
-			(width 0.12)
-			(type solid)
-		)
-		(layer "F.Fab")
-		(uuid "dc6cd189-aed9-4aae-ba90-97ce21a94ecb")
-	)
 	(fp_text user "${REFERENCE}"
-		(at 9.7 0.78 0)
+		(at -2.32 0 0)
 		(layer "F.Fab")
 		(uuid "6913e19c-125a-4190-a2c5-fb2e6a0319fe")
 		(effects
@@ -153,6 +154,7 @@
 				(size 1 1)
 				(thickness 0.15)
 			)
+			(justify right)
 		)
 	)
 	(pad "1" thru_hole circle