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Fix nets, breakaway layout, add schematic

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zyphlar
2026-07-04 03:28:12 -07:00
parent 181558e7aa
commit 3e7d12aa76
6 changed files with 1659 additions and 1066 deletions
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baby-mobile-panel.kicad_pcb
-521
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@@ -1,521 +0,0 @@
(kicad_pcb (version 20221018) (generator "panel_v4")
(general (thickness 1.6))
(paper "A4")
(title_block
(title "Baby Mobile Combined Panel v4")
(date "2026-03-11")
(rev "4.0")
(comment 1 "Carrier: XIAO nRF52840 + IS25LP128F + TPS61220 + FPC-20")
(comment 2 "Adapters: SOP-8, SOP-16N, SOP-16W — castellated, FPC connected")
(comment 3 "Order: JLCPCB, 2-layer, castellated holes=yes, v-score=yes")
)
(layers
(0 "F.Cu" signal) (31 "B.Cu" signal)
(34 "B.Paste" user) (35 "F.Paste" user)
(36 "B.SilkS" user "B.Silkscreen") (37 "F.SilkS" user "F.Silkscreen")
(38 "B.Mask" user "B.Mask") (39 "F.Mask" user "F.Mask")
(44 "Edge.Cuts" user)
(48 "B.Fab" user "B.Fab") (49 "F.Fab" user "F.Fab")
)
(setup
(pad_to_mask_clearance 0.05)
(pcbplotparams (layerselection 0x00010fc_ffffffff) (outputdirectory "gerbers/"))
)
(net 0 "")
(net 1 "GND") (net 2 "VBAT") (net 3 "3V3")
(net 4 "SPI_MOSI") (net 5 "SPI_MISO") (net 6 "SPI_SCK") (net 7 "FLASH_CS")
(net 8 "BOOST_SW") (net 9 "AUDIO_FILT")
(net 10 "S1")
(net 11 "S2")
(net 12 "S3")
(net 13 "S4")
(net 14 "S5")
(net 15 "S6")
(net 16 "S7")
(net 17 "S8")
(net 18 "S9")
(net 19 "S10")
(net 20 "S11")
(net 21 "S12")
(net 22 "S13")
(net 23 "S14")
(net 24 "S15")
(net 25 "S16")
(gr_line (start 100.000 100.000) (end 148.000 100.000) (layer "Edge.Cuts") (width 0.1) (uuid "104212ff-f746-4f58-943d-69bf8fceaca8"))
(gr_line (start 148.000 100.000) (end 148.000 141.000) (layer "Edge.Cuts") (width 0.1) (uuid "3582d3c9-13f0-45b2-adcc-377473ebe9d0"))
(gr_line (start 148.000 141.000) (end 100.000 141.000) (layer "Edge.Cuts") (width 0.1) (uuid "6f73522e-31e6-40f3-bcc3-1fc0e689e4ea"))
(gr_line (start 100.000 141.000) (end 100.000 100.000) (layer "Edge.Cuts") (width 0.1) (uuid "32abf0f8-c4bc-4bb1-b0ff-b04110a51d70"))
(gr_line (start 100.000 126.500) (end 148.000 126.500) (layer "Edge.Cuts") (width 0.1) (uuid "abacf90f-5f8e-4ef2-a121-e18193bb9676"))
(gr_text "▼ SNAP ▼" (at 124.000 126.200) (layer "F.SilkS") (uuid "08a10b1f-8577-4491-91b9-4716c74212a0") (effects (font (size 0.5 0.5) (thickness 0.080))))
(gr_line (start 113.000 127.000) (end 113.000 141.000) (layer "Edge.Cuts") (width 0.1) (uuid "d345fc06-cad9-479e-93ef-620198f44922"))
(gr_line (start 129.000 127.000) (end 129.000 141.000) (layer "Edge.Cuts") (width 0.1) (uuid "dbae9c2c-4bd9-4726-8c84-b1c184d8c290"))
(gr_rect (start 103.000 104.250) (end 124.000 121.750) (layer "F.SilkS") (width 0.2) (uuid "92f1750d-b8eb-47ce-a180-938d8eda924b"))
(gr_rect (start 101.500 108.550) (end 103.000 117.450) (layer "F.SilkS") (width 0.2) (uuid "fa01c07d-7e52-4025-af49-3981a6177d03"))
(gr_rect (start 101.800 108.850) (end 102.900 117.150) (layer "F.SilkS") (width 0.15) (uuid "439700fa-f28d-4385-98da-44b6cda43749"))
(gr_text "USB-C" (at 103.500 113.000) (layer "F.SilkS") (uuid "60eea485-b0b6-45aa-bbf0-1643b0cbc37f") (effects (font (size 0.5 0.5) (thickness 0.080))))
(gr_text "XIAO nRF52840" (at 114.500 113.000) (layer "F.SilkS") (uuid "3adb0e5f-2bbe-4501-87b2-19458737e92a") (effects (font (size 0.8 0.8) (thickness 0.104))))
(gr_text "RST" (at 105.000 105.750) (layer "F.SilkS") (uuid "9b669ce2-3e3d-4a36-b6de-afcd6552af5e") (effects (font (size 0.4 0.4) (thickness 0.080))))
(gr_circle (center 104.000 105.750) (end 104.500 105.750) (layer "F.SilkS") (width 0.1) (fill none) (uuid "419559c3-f3cb-4448-801f-1bc1dc635a8f"))
(footprint "panel:J2_XIAO_L" (layer "F.Cu")
(at 104.610 113.000)
(uuid "1880d745-c8b8-49c4-801a-b7dded7fa4d4")
(fp_text reference "J2_XIAO_L" (at 0 0) (layer "F.Fab") (uuid "e72c399e-a106-4b11-9587-416d6d129d19")
(effects (font (size 0.5 0.5) (thickness 0.08)) hide))
(fp_text value "" (at 0 0) (layer "F.Fab") (uuid "8ecd4411-88bc-41b3-85aa-c4c431acdc2d")
(effects (font (size 0.5 0.5) (thickness 0.08)) hide))
(pad "D0" thru_hole circle (at 0.000 -7.620) (size 1.7 1.7) (drill 1.0) (layers "*.Cu" "*.Mask") (net 10 "S1") (uuid "5f654290-e6f5-4cd1-b3e0-1e01b5e10eee"))
(pad "D1" thru_hole circle (at 0.000 -5.080) (size 1.7 1.7) (drill 1.0) (layers "*.Cu" "*.Mask") (net 11 "S2") (uuid "c221edd1-da4f-427b-834a-117c9d1e8d1b"))
(pad "D2" thru_hole circle (at 0.000 -2.540) (size 1.7 1.7) (drill 1.0) (layers "*.Cu" "*.Mask") (net 12 "S3") (uuid "08153f73-e1a6-455d-8b7a-a176f096ce82"))
(pad "D3" thru_hole circle (at 0.000 0.000) (size 1.7 1.7) (drill 1.0) (layers "*.Cu" "*.Mask") (net 13 "S4") (uuid "5cc418f2-0d3d-46d8-ab1e-da6298ae825b"))
(pad "D4" thru_hole circle (at 0.000 2.540) (size 1.7 1.7) (drill 1.0) (layers "*.Cu" "*.Mask") (net 14 "S5") (uuid "63e8f300-12fc-4b25-864b-a3ce15756f84"))
(pad "D5" thru_hole circle (at 0.000 5.080) (size 1.7 1.7) (drill 1.0) (layers "*.Cu" "*.Mask") (net 15 "S6") (uuid "e116be82-17b5-489e-b602-501c0cb2c5e8"))
(pad "D6" thru_hole circle (at 0.000 7.620) (size 1.7 1.7) (drill 1.0) (layers "*.Cu" "*.Mask") (net 16 "S7") (uuid "12b9d945-953b-4147-abb0-b33958ede447"))
)
(gr_text "D0" (at 102.110 105.380) (layer "F.SilkS") (uuid "062baf94-9f37-4f1b-a75a-447e7bbf4e87") (effects (font (size 0.45 0.45) (thickness 0.080))))
(gr_text "D1" (at 102.110 107.920) (layer "F.SilkS") (uuid "7e51d748-6cf6-4fbe-83a2-e22517497b30") (effects (font (size 0.45 0.45) (thickness 0.080))))
(gr_text "D2" (at 102.110 110.460) (layer "F.SilkS") (uuid "c536f2ba-04dd-469b-86bf-b64989766eaa") (effects (font (size 0.45 0.45) (thickness 0.080))))
(gr_text "D3" (at 102.110 113.000) (layer "F.SilkS") (uuid "fb1f005c-01fe-40b4-9f5e-19520b5e40e6") (effects (font (size 0.45 0.45) (thickness 0.080))))
(gr_text "D4" (at 102.110 115.540) (layer "F.SilkS") (uuid "87c7cbff-7db0-4c52-8c48-617a5fe31e7f") (effects (font (size 0.45 0.45) (thickness 0.080))))
(gr_text "D5" (at 102.110 118.080) (layer "F.SilkS") (uuid "9a253003-4842-4a93-99cf-fb57fcc7cf41") (effects (font (size 0.45 0.45) (thickness 0.080))))
(gr_text "D6" (at 102.110 120.620) (layer "F.SilkS") (uuid "b5b93455-6fbe-4017-ab71-710bfc3c2f9c") (effects (font (size 0.45 0.45) (thickness 0.080))))
(footprint "panel:J3_XIAO_R" (layer "F.Cu")
(at 122.390 113.000)
(uuid "478daaf8-7483-4c18-8d16-3af8d13f1e5a")
(fp_text reference "J3_XIAO_R" (at 0 0) (layer "F.Fab") (uuid "bbc610eb-4935-4d5b-998f-73da0871fd8a")
(effects (font (size 0.5 0.5) (thickness 0.08)) hide))
(fp_text value "" (at 0 0) (layer "F.Fab") (uuid "78b14adf-d763-48b5-830a-4f4a7961ee99")
(effects (font (size 0.5 0.5) (thickness 0.08)) hide))
(pad "D10" thru_hole circle (at 0.000 -7.620) (size 1.7 1.7) (drill 1.0) (layers "*.Cu" "*.Mask") (net 17 "S8") (uuid "59eb4432-199b-4695-a612-a5507fa984d7"))
(pad "D9" thru_hole circle (at 0.000 -5.080) (size 1.7 1.7) (drill 1.0) (layers "*.Cu" "*.Mask") (net 6 "SPI_SCK") (uuid "a57f5812-d1e7-46cd-89f7-6c8d3477a874"))
(pad "D8" thru_hole circle (at 0.000 -2.540) (size 1.7 1.7) (drill 1.0) (layers "*.Cu" "*.Mask") (net 4 "SPI_MOSI") (uuid "0b2075c5-c1ed-4d53-873d-f83ba55d10e9"))
(pad "D7" thru_hole circle (at 0.000 0.000) (size 1.7 1.7) (drill 1.0) (layers "*.Cu" "*.Mask") (net 5 "SPI_MISO") (uuid "5cbd35af-04be-4259-a124-3627c72fea10"))
(pad "3V3" thru_hole circle (at 0.000 2.540) (size 1.7 1.7) (drill 1.0) (layers "*.Cu" "*.Mask") (net 3 "3V3") (uuid "670919f1-8cc6-40c5-98fc-401b537c26c1"))
(pad "GND" thru_hole circle (at 0.000 5.080) (size 1.7 1.7) (drill 1.0) (layers "*.Cu" "*.Mask") (net 1 "GND") (uuid "bd89036b-ac87-476a-89fc-3ea51828db98"))
(pad "5V" thru_hole circle (at 0 7.62) (size 1.7 1.7) (drill 1.0) (layers "*.Cu" "*.Mask") (uuid "f3f13533-e920-4db6-80a9-3517b7a64c80"))
)
(gr_text "D10" (at 125.190 105.380) (layer "F.SilkS") (uuid "4275c31d-9b16-4856-8700-6c07cc109456") (effects (font (size 0.45 0.45) (thickness 0.080))))
(gr_text "D9" (at 125.190 107.920) (layer "F.SilkS") (uuid "69073532-7c55-47b6-a165-1f93082b8c35") (effects (font (size 0.45 0.45) (thickness 0.080))))
(gr_text "D8" (at 125.190 110.460) (layer "F.SilkS") (uuid "b5cae429-dc50-4fe2-9378-264ff635ac1a") (effects (font (size 0.45 0.45) (thickness 0.080))))
(gr_text "D7" (at 125.190 113.000) (layer "F.SilkS") (uuid "71f6b3e5-56d1-4f91-9b80-34363d2cc403") (effects (font (size 0.45 0.45) (thickness 0.080))))
(gr_text "3V3" (at 125.190 115.540) (layer "F.SilkS") (uuid "df934edf-0319-4bd5-ab19-f93733b9b9a4") (effects (font (size 0.45 0.45) (thickness 0.080))))
(gr_text "GND" (at 125.190 118.080) (layer "F.SilkS") (uuid "49eef609-08c6-4002-a11d-552004ad1233") (effects (font (size 0.45 0.45) (thickness 0.080))))
(gr_text "5V" (at 125.190 120.620) (layer "F.SilkS") (uuid "29c03aea-4a86-4e11-a534-6e8a142e738f") (effects (font (size 0.45 0.45) (thickness 0.080))))
(gr_rect (start 129.500 102.300) (end 134.500 108.700) (layer "F.SilkS") (width 0.15) (uuid "ece65163-9657-4253-9e7c-cf0e2df69d41"))
(gr_circle (center 130.500 107.700) (end 130.750 107.700) (layer "F.SilkS") (width 0.1) (fill solid) (uuid "ffc30771-b96d-4890-92ef-8a49a59bf10d"))
(gr_circle (center 132.000 108.700) (end 132.400 108.700) (layer "F.SilkS") (width 0.1) (fill none) (uuid "2cf964ff-8310-4b73-ac5b-8c0325559520"))
(gr_text "U2" (at 132.000 101.300) (layer "F.SilkS") (uuid "4b61fa0a-ae7c-463f-85a2-f1b1079f263a") (effects (font (size 0.5 0.5) (thickness 0.080))))
(gr_text "IS25LP128F" (at 132.000 110.200) (layer "F.SilkS") (uuid "91213253-1da6-483e-9a33-132cc1cfeec0") (effects (font (size 0.4 0.4) (thickness 0.080))))
(gr_text "1" (at 130.095 109.400) (layer "F.SilkS") (uuid "c389beaf-bb8a-42b8-ada0-cead80b18723") (effects (font (size 0.3 0.3) (thickness 0.080))))
(gr_text "2" (at 131.365 109.400) (layer "F.SilkS") (uuid "9a047c7e-335c-40b2-9d91-a0164c53e686") (effects (font (size 0.3 0.3) (thickness 0.080))))
(gr_text "3" (at 132.635 109.400) (layer "F.SilkS") (uuid "acce117a-e72e-48b0-8bbc-7291cc3faed1") (effects (font (size 0.3 0.3) (thickness 0.080))))
(gr_text "4" (at 133.905 109.400) (layer "F.SilkS") (uuid "5d0bfd10-bc74-416b-a1e2-b3ea899497d9") (effects (font (size 0.3 0.3) (thickness 0.080))))
(gr_text "8" (at 130.095 101.600) (layer "F.SilkS") (uuid "eecce093-ba35-41a5-866a-ebf3b5f6bf7e") (effects (font (size 0.3 0.3) (thickness 0.080))))
(gr_text "7" (at 131.365 101.600) (layer "F.SilkS") (uuid "572fb423-e189-4760-be9c-6aa1fe68470e") (effects (font (size 0.3 0.3) (thickness 0.080))))
(gr_text "6" (at 132.635 101.600) (layer "F.SilkS") (uuid "076ee973-262b-4d67-b110-8d39e6bf5aec") (effects (font (size 0.3 0.3) (thickness 0.080))))
(gr_text "5" (at 133.905 101.600) (layer "F.SilkS") (uuid "53062d13-f3c8-4ffc-a340-7303f1916a86") (effects (font (size 0.3 0.3) (thickness 0.080))))
(footprint "panel:U2_Flash" (layer "F.Cu")
(at 132.000 105.500)
(uuid "33f564be-74cb-4b07-9514-48c38bcf8b14")
(fp_text reference "U2_Flash" (at 0 0) (layer "F.Fab") (uuid "2891d898-66a3-4f26-86ab-d7c3390f90b8")
(effects (font (size 0.5 0.5) (thickness 0.08)) hide))
(fp_text value "" (at 0 0) (layer "F.Fab") (uuid "7c379697-fc67-4742-9331-165515e56009")
(effects (font (size 0.5 0.5) (thickness 0.08)) hide))
(pad "1" smd rect (at -1.905 2.700) (size 0.600 1.500) (layers "F.Cu" "F.Paste" "F.Mask") (net 7 "FLASH_CS") (uuid "0f15bea3-f2c1-49e6-97b1-573cd5a98bcd"))
(pad "2" smd rect (at -0.635 2.700) (size 0.600 1.500) (layers "F.Cu" "F.Paste" "F.Mask") (net 5 "SPI_MISO") (uuid "d5cca333-1aa2-4ac6-b73b-2efb9e83ca32"))
(pad "3" smd rect (at 0.635 2.700) (size 0.600 1.500) (layers "F.Cu" "F.Paste" "F.Mask") (net 3 "3V3") (uuid "9af46e90-187d-4c3f-a493-83d009f15909"))
(pad "4" smd rect (at 1.905 2.700) (size 0.600 1.500) (layers "F.Cu" "F.Paste" "F.Mask") (net 1 "GND") (uuid "9a67a279-fb78-4946-be3e-06ab38e9cf5c"))
(pad "5" smd rect (at 1.905 -2.700) (size 0.600 1.500) (layers "F.Cu" "F.Paste" "F.Mask") (net 4 "SPI_MOSI") (uuid "1aa3f49b-ee12-4257-bd98-b46343cb6ec3"))
(pad "6" smd rect (at 0.635 -2.700) (size 0.600 1.500) (layers "F.Cu" "F.Paste" "F.Mask") (net 6 "SPI_SCK") (uuid "e3656871-82ec-4a1f-a339-a99e38566725"))
(pad "7" smd rect (at -0.635 -2.700) (size 0.600 1.500) (layers "F.Cu" "F.Paste" "F.Mask") (net 3 "3V3") (uuid "c01e362b-fa39-45fd-9d08-20192e13cc0e"))
(pad "8" smd rect (at -1.905 -2.700) (size 0.600 1.500) (layers "F.Cu" "F.Paste" "F.Mask") (net 3 "3V3") (uuid "bf52d31d-3fa3-44c6-b949-39bb7be69947"))
)
(footprint "panel:C3" (layer "F.Cu")
(at 137.500 104.500)
(uuid "efd45baf-76b1-41b8-9a69-d16c4aff9996")
(fp_text reference "C3" (at 0 0) (layer "F.Fab") (uuid "a96b08f3-828d-4372-a868-703ccc8aa653")
(effects (font (size 0.5 0.5) (thickness 0.08)) hide))
(fp_text value "" (at 0 0) (layer "F.Fab") (uuid "b58de4ee-0bc1-4028-90e3-53d63e842878")
(effects (font (size 0.5 0.5) (thickness 0.08)) hide))
(pad "1" smd rect (at -1.000 0.000) (size 1.000 1.200) (layers "F.Cu" "F.Paste" "F.Mask") (net 3 "3V3") (uuid "f3c64e10-394d-4f53-8c70-3ebc293cde64"))
(pad "2" smd rect (at 1.000 0.000) (size 1.000 1.200) (layers "F.Cu" "F.Paste" "F.Mask") (net 1 "GND") (uuid "fbdd13da-6c60-4ea6-911e-fe65eede2847"))
)
(gr_text "C3" (at 137.500 103.200) (layer "F.SilkS") (uuid "808da9f5-dde2-4311-8f1f-0a875d9add55") (effects (font (size 0.4 0.4) (thickness 0.080))))
(gr_text "100n" (at 137.500 105.800) (layer "F.SilkS") (uuid "a3914fa0-a733-4591-911f-a6d26678ce2b") (effects (font (size 0.35 0.35) (thickness 0.080))))
(footprint "panel:R2" (layer "F.Cu")
(at 137.500 107.500)
(uuid "4828ff79-0549-47d3-8288-89dd7fd1ffc0")
(fp_text reference "R2" (at 0 0) (layer "F.Fab") (uuid "7807c9fe-f96b-4071-82d0-21ac015980fd")
(effects (font (size 0.5 0.5) (thickness 0.08)) hide))
(fp_text value "" (at 0 0) (layer "F.Fab") (uuid "f3fb6f6e-1ef7-42eb-a348-8b6d7aab4538")
(effects (font (size 0.5 0.5) (thickness 0.08)) hide))
(pad "1" smd rect (at -1.000 0.000) (size 1.000 1.200) (layers "F.Cu" "F.Paste" "F.Mask") (net 7 "FLASH_CS") (uuid "1ccfaa3c-7ea6-4eda-888b-928d091041ad"))
(pad "2" smd rect (at 1.000 0.000) (size 1.000 1.200) (layers "F.Cu" "F.Paste" "F.Mask") (net 3 "3V3") (uuid "f8c4ab39-a4c3-4458-bdd8-29f399b1abee"))
)
(gr_text "R2" (at 137.500 106.300) (layer "F.SilkS") (uuid "c690803d-f367-4a01-baaf-b0f211e95d90") (effects (font (size 0.4 0.4) (thickness 0.080))))
(gr_text "10K" (at 137.500 108.800) (layer "F.SilkS") (uuid "71947797-a79c-4b48-9356-ef04c53cb56e") (effects (font (size 0.35 0.35) (thickness 0.080))))
(footprint "panel:R1" (layer "F.Cu")
(at 132.000 114.000)
(uuid "37cc5e4d-7bf4-41a9-b81e-78764e60f07e")
(fp_text reference "R1" (at 0 0) (layer "F.Fab") (uuid "2ce5f8a6-fc73-4909-a493-fa4121752043")
(effects (font (size 0.5 0.5) (thickness 0.08)) hide))
(fp_text value "" (at 0 0) (layer "F.Fab") (uuid "7e4aacb8-c4cd-441b-8889-70d980a27059")
(effects (font (size 0.5 0.5) (thickness 0.08)) hide))
(pad "1" smd rect (at -1.000 0.000) (size 1.000 1.200) (layers "F.Cu" "F.Paste" "F.Mask") (net 17 "S8") (uuid "8cbfc39f-b0c1-4776-87f0-5c46aa4adca7"))
(pad "2" smd rect (at 1.000 0.000) (size 1.000 1.200) (layers "F.Cu" "F.Paste" "F.Mask") (net 9 "AUDIO_FILT") (uuid "7f43e904-361c-47d3-9be2-9a180465ee3a"))
)
(gr_text "R1 4.7K" (at 132.000 112.700) (layer "F.SilkS") (uuid "60598c4b-e455-4930-9b04-61573d2f5eca") (effects (font (size 0.4 0.4) (thickness 0.080))))
(footprint "panel:C5" (layer "F.Cu")
(at 132.000 117.000)
(uuid "c2dc742d-aa63-4e4f-937b-6eca10fc9c75")
(fp_text reference "C5" (at 0 0) (layer "F.Fab") (uuid "3a7604db-e795-488a-81b5-f79e4a9493dd")
(effects (font (size 0.5 0.5) (thickness 0.08)) hide))
(fp_text value "" (at 0 0) (layer "F.Fab") (uuid "68eb2d54-0fbe-4929-a0a8-f4257e22fdb0")
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(pad "11" thru_hole circle (at 1.905 -5.150) (size 1.0 1.0) (drill 0.6) (layers "*.Cu" "*.Mask") (net 20 "S11") (uuid "d17321cf-ade0-45fb-aeee-06e5fdaa68e7"))
(pad "7" thru_hole circle (at 3.175 5.150) (size 1.0 1.0) (drill 0.6) (layers "*.Cu" "*.Mask") (net 16 "S7") (uuid "bbe5650f-8272-4951-826c-0219408d73cd"))
(pad "10" thru_hole circle (at 3.175 -5.150) (size 1.0 1.0) (drill 0.6) (layers "*.Cu" "*.Mask") (net 19 "S10") (uuid "63cb5f6b-69ec-4b02-a58d-0f747f085670"))
(pad "8" thru_hole circle (at 4.445 5.150) (size 1.0 1.0) (drill 0.6) (layers "*.Cu" "*.Mask") (net 17 "S8") (uuid "41ec5aee-f8ba-4088-8232-1c50ad81a9d8"))
(pad "9" thru_hole circle (at 4.445 -5.150) (size 1.0 1.0) (drill 0.6) (layers "*.Cu" "*.Mask") (net 18 "S9") (uuid "4cdbd15b-f470-4028-aa99-11f1bc409fce"))
)
(gr_text "1" (at 132.555 139.850) (layer "F.SilkS") (uuid "903925f1-1ab0-4ef8-8091-eee1ba4ce83c") (effects (font (size 0.3 0.3) (thickness 0.080))))
(gr_text "16" (at 132.555 128.150) (layer "F.SilkS") (uuid "da86f49d-5143-47ea-b69d-4b9832fead6f") (effects (font (size 0.3 0.3) (thickness 0.080))))
(gr_text "2" (at 133.825 139.850) (layer "F.SilkS") (uuid "574499ab-7233-4486-83cb-f54f410f254c") (effects (font (size 0.3 0.3) (thickness 0.080))))
(gr_text "15" (at 133.825 128.150) (layer "F.SilkS") (uuid "abab922c-b06d-42a5-a83f-dd0fdee84413") (effects (font (size 0.3 0.3) (thickness 0.080))))
(gr_text "3" (at 135.095 139.850) (layer "F.SilkS") (uuid "a7206bb0-3b93-40f7-b721-b0f8e559a08a") (effects (font (size 0.3 0.3) (thickness 0.080))))
(gr_text "14" (at 135.095 128.150) (layer "F.SilkS") (uuid "7554af84-eaab-46e6-a23b-61be3208358c") (effects (font (size 0.3 0.3) (thickness 0.080))))
(gr_text "4" (at 136.365 139.850) (layer "F.SilkS") (uuid "754ceb56-2739-4ffb-95b6-f74fec1b55fe") (effects (font (size 0.3 0.3) (thickness 0.080))))
(gr_text "13" (at 136.365 128.150) (layer "F.SilkS") (uuid "8eba4921-1108-42f3-a832-725064d0b8a9") (effects (font (size 0.3 0.3) (thickness 0.080))))
(gr_text "5" (at 137.635 139.850) (layer "F.SilkS") (uuid "39081f0f-c80d-4f8e-93ab-18f7d2073f11") (effects (font (size 0.3 0.3) (thickness 0.080))))
(gr_text "12" (at 137.635 128.150) (layer "F.SilkS") (uuid "4fafe525-5c4a-4ad0-a9bd-fa1b7525e18c") (effects (font (size 0.3 0.3) (thickness 0.080))))
(gr_text "6" (at 138.905 139.850) (layer "F.SilkS") (uuid "4de276b8-3628-4e51-91a7-ccc54c74f700") (effects (font (size 0.3 0.3) (thickness 0.080))))
(gr_text "11" (at 138.905 128.150) (layer "F.SilkS") (uuid "d27ef244-2781-49c2-9afe-ea795a76c9e0") (effects (font (size 0.3 0.3) (thickness 0.080))))
(gr_text "7" (at 140.175 139.850) (layer "F.SilkS") (uuid "a5febf7b-e28d-475b-9d51-13676d8adec6") (effects (font (size 0.3 0.3) (thickness 0.080))))
(gr_text "10" (at 140.175 128.150) (layer "F.SilkS") (uuid "84b49153-2c4a-4ece-8a04-6b499665a85c") (effects (font (size 0.3 0.3) (thickness 0.080))))
(gr_text "8" (at 141.445 139.850) (layer "F.SilkS") (uuid "a2b8a7f3-e99c-4581-86b4-3fd69ba4a35a") (effects (font (size 0.3 0.3) (thickness 0.080))))
(gr_text "9" (at 141.445 128.150) (layer "F.SilkS") (uuid "c05f3d6b-67d3-4d21-a81e-3839951a4f75") (effects (font (size 0.3 0.3) (thickness 0.080))))
(gr_circle (center 132.055 139.650) (end 132.255 139.650) (layer "F.SilkS") (width 0.1) (fill solid) (uuid "c9f11721-a6fa-42bc-befe-e2f4dd6eaf33"))
(gr_text "●1" (at 132.055 140.450) (layer "F.SilkS") (uuid "3b2f91bf-64bb-4074-ab2b-bfe789fec0a6") (effects (font (size 0.3 0.3) (thickness 0.080))))
(gr_text "SOP-16W ●1→" (at 137.000 134.000) (layer "B.SilkS") (uuid "8e3f70e7-d940-41f4-8f33-40a7fedc23e1") (effects (font (size 0.5 0.5) (thickness 0.080)) (justify mirror)))
(footprint "panel:SOP-16W_FPC" (layer "F.Cu")
(at 137.000 134.000)
(uuid "5478245e-9ede-494c-86f7-8c704435e999")
(fp_text reference "SOP-16W_FPC" (at 0 0) (layer "F.Fab") (uuid "2a4de4cb-a137-40c1-abd2-23c8d6f4a50e")
(effects (font (size 0.5 0.5) (thickness 0.08)) hide))
(fp_text value "" (at 0 0) (layer "F.Fab") (uuid "c72e6768-7d5d-4b2e-b8cc-c93c7f06de68")
(effects (font (size 0.5 0.5) (thickness 0.08)) hide))
(pad "F1" smd rect (at -4.750 0.000) (size 0.300 1.000) (layers "F.Cu" "F.Paste" "F.Mask") (net 10 "S1") (uuid "4df4fcc1-91f4-4143-a052-5d489d23ba9e"))
(pad "F2" smd rect (at -4.250 0.000) (size 0.300 1.000) (layers "F.Cu" "F.Paste" "F.Mask") (net 11 "S2") (uuid "99e5aca1-d974-42e7-bd70-3947a4c12696"))
(pad "F3" smd rect (at -3.750 0.000) (size 0.300 1.000) (layers "F.Cu" "F.Paste" "F.Mask") (net 12 "S3") (uuid "f1cbc508-4e8b-4b32-bf5e-720b074714a1"))
(pad "F4" smd rect (at -3.250 0.000) (size 0.300 1.000) (layers "F.Cu" "F.Paste" "F.Mask") (net 13 "S4") (uuid "674c45c4-5c55-40a1-a9d2-6b3ed7341da9"))
(pad "F5" smd rect (at -2.750 0.000) (size 0.300 1.000) (layers "F.Cu" "F.Paste" "F.Mask") (net 14 "S5") (uuid "337b151c-41af-467f-87b2-00234db90bc2"))
(pad "F6" smd rect (at -2.250 0.000) (size 0.300 1.000) (layers "F.Cu" "F.Paste" "F.Mask") (net 15 "S6") (uuid "db978209-cdee-4ef7-af46-de8b822bbe8e"))
(pad "F7" smd rect (at -1.750 0.000) (size 0.300 1.000) (layers "F.Cu" "F.Paste" "F.Mask") (net 16 "S7") (uuid "e1d6460e-2b6d-46b4-b939-75c0977105d2"))
(pad "F8" smd rect (at -1.250 0.000) (size 0.300 1.000) (layers "F.Cu" "F.Paste" "F.Mask") (net 17 "S8") (uuid "577260c3-7e9a-4765-8b88-c508c82ca5fe"))
(pad "F9" smd rect (at -0.750 0.000) (size 0.300 1.000) (layers "F.Cu" "F.Paste" "F.Mask") (net 18 "S9") (uuid "4b3b0582-a33d-4365-888e-d1d87161e6f9"))
(pad "F10" smd rect (at -0.250 0.000) (size 0.300 1.000) (layers "F.Cu" "F.Paste" "F.Mask") (net 19 "S10") (uuid "d76146ee-cf79-4036-88c0-20f702a2d563"))
(pad "F11" smd rect (at 0.250 0.000) (size 0.300 1.000) (layers "F.Cu" "F.Paste" "F.Mask") (net 20 "S11") (uuid "e4e0ff0d-fc4f-4c4e-bbbf-aa1ca1b1c93a"))
(pad "F12" smd rect (at 0.750 0.000) (size 0.300 1.000) (layers "F.Cu" "F.Paste" "F.Mask") (net 21 "S12") (uuid "b0734618-3cdf-45c4-ba08-e3388c711631"))
(pad "F13" smd rect (at 1.250 0.000) (size 0.300 1.000) (layers "F.Cu" "F.Paste" "F.Mask") (net 22 "S13") (uuid "dda517bb-3b46-438f-8d3f-2dfa9a5b3245"))
(pad "F14" smd rect (at 1.750 0.000) (size 0.300 1.000) (layers "F.Cu" "F.Paste" "F.Mask") (net 23 "S14") (uuid "abace38a-0077-4aaf-a85a-6ff5e8583256"))
(pad "F15" smd rect (at 2.250 0.000) (size 0.300 1.000) (layers "F.Cu" "F.Paste" "F.Mask") (net 24 "S15") (uuid "7909ec78-3977-4645-a41f-da0b47002a7e"))
(pad "F16" smd rect (at 2.750 0.000) (size 0.300 1.000) (layers "F.Cu" "F.Paste" "F.Mask") (net 25 "S16") (uuid "c83088b7-ac0b-4663-b84e-feef5eeb0723"))
(pad "F17" smd rect (at 3.250 0.000) (size 0.300 1.000) (layers "F.Cu" "F.Paste" "F.Mask") (net 0 "") (uuid "a7bda6dd-b3b3-47e9-b511-fcb766a1837a"))
(pad "F18" smd rect (at 3.750 0.000) (size 0.300 1.000) (layers "F.Cu" "F.Paste" "F.Mask") (net 0 "") (uuid "89ad3bdd-bdf4-4183-9438-c2e232e12f60"))
(pad "F19" smd rect (at 4.250 0.000) (size 0.300 1.000) (layers "F.Cu" "F.Paste" "F.Mask") (net 1 "GND") (uuid "4d94e0ec-cf5e-4e0d-90c7-67e79b8895fa"))
(pad "F20" smd rect (at 4.750 0.000) (size 0.300 1.000) (layers "F.Cu" "F.Paste" "F.Mask") (net 2 "VBAT") (uuid "bdf4aaea-e105-4332-8cc8-e82574c5981d"))
(pad "SA" smd rect (at -6.250 1.500) (size 1.200 0.800) (layers "F.Cu" "F.Paste" "F.Mask") (net 0 "") (uuid "bec1c65a-3746-408f-8e77-1658a529d58f"))
(pad "SB" smd rect (at 6.250 1.500) (size 1.200 0.800) (layers "F.Cu" "F.Paste" "F.Mask") (net 0 "") (uuid "68022482-2ede-4193-8fcc-50f4c15238fc"))
)
(gr_text "FPC" (at 137.000 132.200) (layer "F.SilkS") (uuid "3c9ae79a-befd-49b6-89e8-48dfbfb5a408") (effects (font (size 0.35 0.35) (thickness 0.080))))
(gr_circle (center 131.650 134.000) (end 131.800 134.000) (layer "F.SilkS") (width 0.1) (fill solid) (uuid "1554c550-4b83-40cc-8602-7a4138599540"))
(gr_text "Baby Mobile v4 — JLCPCB Panel" (at 124.000 98.000) (layer "F.SilkS") (uuid "02d054e6-07a0-4ad2-a9a2-903bf039b5bc") (effects (font (size 1.0 1.0) (thickness 0.130))))
(gr_text "Castellated Holes=YES V-Score=YES 2-Layer 1.6mm" (at 124.000 143.000) (layer "F.SilkS") (uuid "1a248073-4356-45d5-9f5d-0b7d77830e4a") (effects (font (size 0.5 0.5) (thickness 0.080))))
)
baby-mobile-v5.kicad_pcb
+613
View File
@@ -0,0 +1,613 @@
(kicad_pcb (version 20221018) (generator "bm_v5")
(general (thickness 1.6))
(paper "A4")
(title_block
(title "Baby Mobile v5 — Key-Shaped Panel")
(date "2026-03-11") (rev "5.0")
(comment 1 "Carrier head + breakaway adapter stem")
(comment 2 "Unique nets per sub-board, FPC interconnect")
)
(layers
(0 "F.Cu" signal) (31 "B.Cu" signal)
(34 "B.Paste" user) (35 "F.Paste" user)
(36 "B.SilkS" user "B.Silkscreen") (37 "F.SilkS" user "F.Silkscreen")
(38 "B.Mask" user "B.Mask") (39 "F.Mask" user "F.Mask")
(44 "Edge.Cuts" user)
(48 "B.Fab" user "B.Fab") (49 "F.Fab" user "F.Fab")
)
(net 0 "")
(net 1 "GND")
(net 2 "C_VBAT")
(net 3 "C_3V3")
(net 4 "BOOST_SW")
(net 5 "AUDIO_FILT")
(net 6 "SPI_MOSI")
(net 7 "SPI_MISO")
(net 8 "SPI_SCK")
(net 9 "FLASH_CS")
(net 10 "C_S1")
(net 11 "C_S2")
(net 12 "C_S3")
(net 13 "C_S4")
(net 14 "C_S5")
(net 15 "C_S6")
(net 16 "C_S7")
(net 17 "C_S8")
(net 18 "FPC_C1")
(net 19 "FPC_C2")
(net 20 "FPC_C3")
(net 21 "FPC_C4")
(net 22 "FPC_C5")
(net 23 "FPC_C6")
(net 24 "FPC_C7")
(net 25 "FPC_C8")
(net 26 "FPC_C9")
(net 27 "FPC_C10")
(net 28 "FPC_C11")
(net 29 "FPC_C12")
(net 30 "FPC_C13")
(net 31 "FPC_C14")
(net 32 "FPC_C15")
(net 33 "FPC_C16")
(net 34 "FPC_C17")
(net 35 "FPC_C18")
(net 36 "FPC_C19")
(net 37 "FPC_C20")
(net 38 "A8_P1")
(net 39 "A8_P2")
(net 40 "A8_P3")
(net 41 "A8_P4")
(net 42 "A8_P5")
(net 43 "A8_P6")
(net 44 "A8_P7")
(net 45 "A8_P8")
(net 46 "A8_VBAT")
(net 47 "A8_GND")
(net 48 "FPC_A8_1")
(net 49 "FPC_A8_2")
(net 50 "FPC_A8_3")
(net 51 "FPC_A8_4")
(net 52 "FPC_A8_5")
(net 53 "FPC_A8_6")
(net 54 "FPC_A8_7")
(net 55 "FPC_A8_8")
(net 56 "FPC_A8_9")
(net 57 "FPC_A8_10")
(net 58 "A16N_P1")
(net 59 "A16N_P2")
(net 60 "A16N_P3")
(net 61 "A16N_P4")
(net 62 "A16N_P5")
(net 63 "A16N_P6")
(net 64 "A16N_P7")
(net 65 "A16N_P8")
(net 66 "A16N_P9")
(net 67 "A16N_P10")
(net 68 "A16N_P11")
(net 69 "A16N_P12")
(net 70 "A16N_P13")
(net 71 "A16N_P14")
(net 72 "A16N_P15")
(net 73 "A16N_P16")
(net 74 "A16N_VBAT")
(net 75 "A16N_GND")
(net 76 "FPC_A16N_1")
(net 77 "FPC_A16N_2")
(net 78 "FPC_A16N_3")
(net 79 "FPC_A16N_4")
(net 80 "FPC_A16N_5")
(net 81 "FPC_A16N_6")
(net 82 "FPC_A16N_7")
(net 83 "FPC_A16N_8")
(net 84 "FPC_A16N_9")
(net 85 "FPC_A16N_10")
(net 86 "FPC_A16N_11")
(net 87 "FPC_A16N_12")
(net 88 "FPC_A16N_13")
(net 89 "FPC_A16N_14")
(net 90 "FPC_A16N_15")
(net 91 "FPC_A16N_16")
(net 92 "FPC_A16N_17")
(net 93 "FPC_A16N_18")
(net 94 "FPC_A16N_19")
(net 95 "FPC_A16N_20")
(net 96 "A16W_P1")
(net 97 "A16W_P2")
(net 98 "A16W_P3")
(net 99 "A16W_P4")
(net 100 "A16W_P5")
(net 101 "A16W_P6")
(net 102 "A16W_P7")
(net 103 "A16W_P8")
(net 104 "A16W_P9")
(net 105 "A16W_P10")
(net 106 "A16W_P11")
(net 107 "A16W_P12")
(net 108 "A16W_P13")
(net 109 "A16W_P14")
(net 110 "A16W_P15")
(net 111 "A16W_P16")
(net 112 "A16W_VBAT")
(net 113 "A16W_GND")
(net 114 "FPC_A16W_1")
(net 115 "FPC_A16W_2")
(net 116 "FPC_A16W_3")
(net 117 "FPC_A16W_4")
(net 118 "FPC_A16W_5")
(net 119 "FPC_A16W_6")
(net 120 "FPC_A16W_7")
(net 121 "FPC_A16W_8")
(net 122 "FPC_A16W_9")
(net 123 "FPC_A16W_10")
(net 124 "FPC_A16W_11")
(net 125 "FPC_A16W_12")
(net 126 "FPC_A16W_13")
(net 127 "FPC_A16W_14")
(net 128 "FPC_A16W_15")
(net 129 "FPC_A16W_16")
(net 130 "FPC_A16W_17")
(net 131 "FPC_A16W_18")
(net 132 "FPC_A16W_19")
(net 133 "FPC_A16W_20")
(setup (pad_to_mask_clearance 0.05)
(pcbplotparams (layerselection 0x00010fc_ffffffff) (outputdirectory "gerbers/")))
(gr_line (start 100.000 100.000) (end 126.000 100.000) (layer "Edge.Cuts") (width 0.1) (uuid "4d661e2a-9510-461b-8504-90f994722549"))
(gr_line (start 126.000 100.000) (end 126.000 124.000) (layer "Edge.Cuts") (width 0.1) (uuid "b6a3f7d2-4c68-4ecc-b5c3-5fb65b525c78"))
(gr_line (start 126.000 124.000) (end 120.000 124.000) (layer "Edge.Cuts") (width 0.1) (uuid "b6a457b6-5caf-4e28-9260-481968dead15"))
(gr_line (start 120.000 124.000) (end 120.000 156.000) (layer "Edge.Cuts") (width 0.1) (uuid "97a94f6a-2664-4c31-815d-20f12b369994"))
(gr_line (start 120.000 156.000) (end 106.000 156.000) (layer "Edge.Cuts") (width 0.1) (uuid "ab567175-e60f-4630-94cb-2020237ce09b"))
(gr_line (start 106.000 156.000) (end 106.000 124.000) (layer "Edge.Cuts") (width 0.1) (uuid "861d5736-f347-4632-af8e-69c13686e9a9"))
(gr_line (start 106.000 124.000) (end 100.000 124.000) (layer "Edge.Cuts") (width 0.1) (uuid "7bf4650b-dd82-449c-b095-18d174f5f0c9"))
(gr_line (start 100.000 124.000) (end 100.000 100.000) (layer "Edge.Cuts") (width 0.1) (uuid "8268d642-8255-4d5f-8830-3bd339f1ab0f"))
(gr_line (start 106.000 132.000) (end 120.000 132.000) (layer "Edge.Cuts") (width 0.1) (uuid "eb4f805a-3060-4d03-8d53-57533430963f"))
(gr_line (start 106.000 142.000) (end 120.000 142.000) (layer "Edge.Cuts") (width 0.1) (uuid "40ac3a54-0553-46fe-95c6-e92c688905d0"))
(gr_text "SNAP" (at 113.000 131.700) (layer "F.SilkS") (uuid "29097a4f-cad7-4970-bcd5-60ea382323c3") (effects (font (size 0.4 0.4) (thickness 0.080))))
(gr_text "SNAP" (at 113.000 141.700) (layer "F.SilkS") (uuid "d3f74d74-3e23-4b89-861c-7c2370be3d35") (effects (font (size 0.4 0.4) (thickness 0.080))))
(gr_rect (start 104.250 101.500) (end 121.750 122.500) (layer "F.SilkS") (width 0.2) (uuid "1a2aa14c-38b9-4c8f-a464-794909866483"))
(gr_rect (start 108.550 98.300) (end 117.450 101.500) (layer "F.SilkS") (width 0.2) (uuid "30e02621-4bc8-4fa3-9af9-cc7dc5e650d9"))
(gr_text "USB-C" (at 113.000 99.900) (layer "F.SilkS") (uuid "1a4672f7-33d3-4241-b27e-5dd8780886b4") (effects (font (size 0.45 0.45) (thickness 0.080))))
(gr_text "XIAO nRF52840" (at 113.000 112.000) (layer "F.SilkS") (uuid "e97ffc86-50b8-4c2a-b0a9-1c03b8a08668") (effects (font (size 0.6 0.6) (thickness 0.080))))
(gr_text "RST" (at 106.250 103.000) (layer "F.SilkS") (uuid "ac56f812-ff40-4033-966c-e4616002c6e7") (effects (font (size 0.35 0.35) (thickness 0.080))))
(footprint "bm:XIAO_L" (layer "F.Cu")
(at 105.500 104.500)
(uuid "551872f2-8dee-4593-b20c-796277d6acc3")
(fp_text reference "XIAO_L" (at 0 0) (layer "F.Fab") (uuid "d4e3b7a8-59d4-489e-b2a5-b7af2e7a0181")
(effects (font (size 0.5 0.5) (thickness 0.08)) hide))
(fp_text value "" (at 0 0) (layer "F.Fab") (uuid "425c0bee-1bc3-4f73-af00-955a63070d8d")
(effects (font (size 0.5 0.5) (thickness 0.08)) hide))
(pad "D0" thru_hole circle (at 0.000 0.000) (size 1.7 1.7) (drill 1.0) (layers "*.Cu" "*.Mask") (net 10 "C_S1") (uuid "918edf81-9320-40a2-8c80-1162f8938b60"))
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(pad "F13" smd rect (at 1.250 0.000) (size 0.300 1.000) (layers "F.Cu" "F.Paste" "F.Mask") (net 126 "FPC_A16W_13") (uuid "360b448b-93a8-4b26-a64a-4979b29df940"))
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(pad "SA" smd rect (at -6.000 1.500) (size 1.200 0.800) (layers "F.Cu" "F.Paste" "F.Mask") (net 0 "") (uuid "9718e42f-cd94-4536-bb3b-22c35a22d355"))
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)
(gr_text "FPC" (at 113.000 147.500) (layer "F.SilkS") (uuid "4f14f339-bb71-4185-b05a-ff9db5cc6780") (effects (font (size 0.3 0.3) (thickness 0.080))))
(gr_circle (center 107.750 149.000) (end 107.900 149.000) (layer "F.SilkS") (width 0.1) (fill solid) (uuid "c91f59ef-7ee2-43b6-abcf-161d422ea4c3"))
(gr_text "Baby Mobile v5 — github.com/you/baby-mobile" (at 113.000 112.000) (layer "B.SilkS") (uuid "ab2d28e7-e371-4dce-8027-69df7d50f77c") (effects (font (size 0.4 0.4) (thickness 0.080))))
)
baby-mobile-panel.kicad_pro → baby-mobile-v5.kicad_pro
+8 -2
View File
@@ -1,12 +1,13 @@
{
"meta": {
"filename": "baby-mobile-panel.kicad_pro",
"filename": "baby-mobile-v5.kicad_pro",
"version": 1
},
"board": {
"design_settings": {
"rules": {
"min_track_width": 0.15
"min_track_width": 0.15,
"min_via_diameter": 0.4
}
}
},
@@ -16,6 +17,11 @@
"name": "Default",
"clearance": 0.15,
"track_width": 0.25
},
{
"name": "Power",
"clearance": 0.2,
"track_width": 0.5
}
]
}
baby-mobile-v5.kicad_sch
+318
View File
@@ -0,0 +1,318 @@
(kicad_sch (version 20230121) (generator "bm_v5_sch")
(uuid "3033f063-d051-4b2e-89f5-f1cfe4577b32")
(paper "A3")
(title_block
(title "Baby Mobile v5 — Schematic")
(date "2026-03-11") (rev "5.0")
(comment 1 "XIAO nRF52840 + IS25LP128F + TPS61220")
(comment 2 "Key-shaped panel with breakaway SOP adapters")
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(property "Reference" "C3" (at 213 67 0) (effects (font (size 1.27 1.27))))
(property "Value" "100nF" (at 213 73 0) (effects (font (size 1.27 1.27))))
(property "Footprint" "Capacitor_SMD:C_0805_2012Metric" (at 210 70 0) (effects (font (size 1.27 1.27)) hide))
(property "Datasheet" "" (at 210 70 0) (effects (font (size 1.27 1.27)) hide))
)
(symbol (lib_id "bm:L") (at 180 115 0) (unit 1)
(in_bom yes) (on_board yes) (dnp no)
(uuid "c358b595-8b13-497e-9e9e-49f65d43ca20")
(property "Reference" "L1" (at 183 112 0) (effects (font (size 1.27 1.27))))
(property "Value" "4.7uH" (at 183 118 0) (effects (font (size 1.27 1.27))))
(property "Footprint" "Inductor_SMD:L_0805_2012Metric" (at 180 115 0) (effects (font (size 1.27 1.27)) hide))
(property "Datasheet" "" (at 180 115 0) (effects (font (size 1.27 1.27)) hide))
)
(symbol (lib_id "bm:C") (at 160 140 0) (unit 1)
(in_bom yes) (on_board yes) (dnp no)
(uuid "be44b856-bd18-4c09-9ee0-04202caf4768")
(property "Reference" "C1" (at 163 137 0) (effects (font (size 1.27 1.27))))
(property "Value" "10uF" (at 163 143 0) (effects (font (size 1.27 1.27))))
(property "Footprint" "Capacitor_SMD:C_0805_2012Metric" (at 160 140 0) (effects (font (size 1.27 1.27)) hide))
(property "Datasheet" "" (at 160 140 0) (effects (font (size 1.27 1.27)) hide))
)
(symbol (lib_id "bm:C") (at 200 140 0) (unit 1)
(in_bom yes) (on_board yes) (dnp no)
(uuid "d225c3fa-9586-478d-a854-6d14dbaa4bfd")
(property "Reference" "C2" (at 203 137 0) (effects (font (size 1.27 1.27))))
(property "Value" "10uF" (at 203 143 0) (effects (font (size 1.27 1.27))))
(property "Footprint" "Capacitor_SMD:C_0805_2012Metric" (at 200 140 0) (effects (font (size 1.27 1.27)) hide))
(property "Datasheet" "" (at 200 140 0) (effects (font (size 1.27 1.27)) hide))
)
(symbol (lib_id "bm:FPC_10") (at 280 80 0) (unit 1)
(in_bom yes) (on_board yes) (dnp no)
(uuid "dbdc9c1a-6b0f-497d-87bf-2ba4cae89123")
(property "Reference" "J2" (at 283 77 0) (effects (font (size 1.27 1.27))))
(property "Value" "FPC-10 SOP-8" (at 283 83 0) (effects (font (size 1.27 1.27))))
(property "Footprint" "" (at 280 80 0) (effects (font (size 1.27 1.27)) hide))
(property "Datasheet" "" (at 280 80 0) (effects (font (size 1.27 1.27)) hide))
)
(symbol (lib_id "bm:FPC_20") (at 280 140 0) (unit 1)
(in_bom yes) (on_board yes) (dnp no)
(uuid "1e20e107-cee6-42e8-a075-64e6e08c59d3")
(property "Reference" "J3" (at 283 137 0) (effects (font (size 1.27 1.27))))
(property "Value" "FPC-20 SOP-16N" (at 283 143 0) (effects (font (size 1.27 1.27))))
(property "Footprint" "" (at 280 140 0) (effects (font (size 1.27 1.27)) hide))
(property "Datasheet" "" (at 280 140 0) (effects (font (size 1.27 1.27)) hide))
)
(symbol (lib_id "bm:FPC_20") (at 280 200 0) (unit 1)
(in_bom yes) (on_board yes) (dnp no)
(uuid "088f021c-2eb1-4377-ac14-7c561fdd9f65")
(property "Reference" "J4" (at 283 197 0) (effects (font (size 1.27 1.27))))
(property "Value" "FPC-20 SOP-16W" (at 283 203 0) (effects (font (size 1.27 1.27))))
(property "Footprint" "" (at 280 200 0) (effects (font (size 1.27 1.27)) hide))
(property "Datasheet" "" (at 280 200 0) (effects (font (size 1.27 1.27)) hide))
)
(label "SPI_SCK" (at 95 67.5 0) (effects (font (size 1.27 1.27))) (uuid "c42549fd-10be-4aad-afc7-8c810f319c36"))
(label "SPI_SCK" (at 190 58.5 0) (effects (font (size 1.27 1.27))) (uuid "b54a8fdc-6ac2-449c-ba67-22dc6766d98b"))
(label "SPI_MOSI" (at 95 70 0) (effects (font (size 1.27 1.27))) (uuid "fa1c1149-1576-4e88-8b85-a0eb1619bcea"))
(label "SPI_MOSI" (at 190 56 0) (effects (font (size 1.27 1.27))) (uuid "b88e4cf0-f774-4040-a7c2-24b10243d283"))
(label "SPI_MISO" (at 95 72.5 0) (effects (font (size 1.27 1.27))) (uuid "93297208-6d7b-4f46-888b-3eacc4f07f2d"))
(label "SPI_MISO" (at 170 61.5 0) (effects (font (size 1.27 1.27))) (uuid "7cc87975-f349-405a-8a10-37857fc82f63"))
(label "FLASH_CS" (at 170 64 0) (effects (font (size 1.27 1.27))) (uuid "7c602734-cf64-4579-b740-428c9d1bf4ca"))
(label "FLASH_CS" (at 210 45 0) (effects (font (size 1.27 1.27))) (uuid "71348c34-2666-48f0-a1d7-74038192d9ac"))
(label "C_3V3" (at 95 77.5 0) (effects (font (size 1.27 1.27))) (uuid "ee3c2698-ac21-4e70-a3c2-b7bf2488d174"))
(label "C_3V3" (at 190 64 0) (effects (font (size 1.27 1.27))) (uuid "0495d91b-e07e-42f8-97b5-e0f3ba1e8f04"))
(label "C_3V3" (at 190 133 0) (effects (font (size 1.27 1.27))) (uuid "3a6f36f4-a58d-4526-bbef-9adda98bf7c0"))
(label "GND" (at 95 80 0) (effects (font (size 1.27 1.27))) (uuid "5871e4a9-6710-4460-a682-9a0067aebbbf"))
(label "GND" (at 170 56 0) (effects (font (size 1.27 1.27))) (uuid "4efb8414-a693-4e31-a3f5-6fce8f1df21d"))
(label "GND" (at 170 127 0) (effects (font (size 1.27 1.27))) (uuid "018eeef1-8d0f-4e97-bfa8-f51f977577bf"))
(label "C_S1" (at 65 65 0) (effects (font (size 1.27 1.27))) (uuid "f644a442-355d-445d-8c08-7729fe701df7"))
(label "C_S2" (at 65 67.5 0) (effects (font (size 1.27 1.27))) (uuid "4d5124ce-b786-4ad8-92cd-20d493231b0f"))
(label "C_S3" (at 65 70 0) (effects (font (size 1.27 1.27))) (uuid "c15ff5c5-329a-4e35-a245-17f45d0f44c2"))
(label "C_S4" (at 65 72.5 0) (effects (font (size 1.27 1.27))) (uuid "7bc33049-5614-4b6a-98d5-8d6bcd9cb33e"))
(label "C_S5" (at 65 75 0) (effects (font (size 1.27 1.27))) (uuid "6e057bfa-6ec0-4b17-b32b-e4fa2dac8adb"))
(label "C_S6" (at 65 77.5 0) (effects (font (size 1.27 1.27))) (uuid "daf90d30-c0ba-4d82-8d00-7786902375c6"))
(label "C_S7" (at 65 80 0) (effects (font (size 1.27 1.27))) (uuid "f4d53fcf-2294-4087-adaa-5868e3e1cae4"))
(label "C_S8" (at 95 65 0) (effects (font (size 1.27 1.27))) (uuid "2392265d-3aa6-435c-955f-300296cebda5"))
(label "C_S8" (at 130 80 0) (effects (font (size 1.27 1.27))) (uuid "220dfbea-98b7-4cf5-9387-f4610df10a5d"))
(label "AUDIO_FILT" (at 150 80 0) (effects (font (size 1.27 1.27))) (uuid "652c7bf4-9751-42e0-8fcd-2d704769d29e"))
(label "C_VBAT" (at 170 133 0) (effects (font (size 1.27 1.27))) (uuid "38617934-d4a7-466c-9079-41ca1565072a"))
(label "C_VBAT" (at 180 110 0) (effects (font (size 1.27 1.27))) (uuid "af0e9186-887c-4293-8f51-af66874d2bd7"))
(label "BOOST_SW" (at 180 122 0) (effects (font (size 1.27 1.27))) (uuid "600b6dba-ff8f-449e-8d13-43f8afb71ade"))
(label "BOOST_SW" (at 180 120 0) (effects (font (size 1.27 1.27))) (uuid "caaed790-ed9a-4383-9419-464e625cd094"))
(text "CARRIER: XIAO nRF52840 + IS25LP128F (16MB) + TPS61220 (3.3V boost)" (at 40 30 0) (effects (font (size 1.5 1.5)) (justify left)) (uuid "f65d8fb2-42b9-41bd-9d1f-2510573aad78"))
(text "FPC-20 cable connects carrier to one of the SOP adapter boards" (at 40 35 0) (effects (font (size 1.5 1.5)) (justify left)) (uuid "54d89a0d-93b5-4be0-b8c6-e10b5bb24ab7"))
(text "ADAPTERS: Snap-off castellated SOP footprints" (at 250 30 0) (effects (font (size 1.5 1.5)) (justify left)) (uuid "5dc73088-8f3a-4c90-98e7-1b7f701966f9"))
(text "Each has its own FPC connector + unique net names" (at 250 35 0) (effects (font (size 1.5 1.5)) (justify left)) (uuid "8947ecc0-f63e-46c6-aef9-f5acf6373af4"))
)
generate_panel.py
-543
View File
@@ -1,543 +0,0 @@
#!/usr/bin/env python3
"""
Baby Mobile — Combined Panel v4
PANEL LAYOUT:
┌───────────────────────────────────────────────┐
│ CARRIER BOARD (44×26mm) │
│ ┌───────USB-C──┐ │
│ │ █████████████ │ │
│ │ │ [U2 IS25LP128F] [C3][R2] │
│ │ XIAO BLE │ ●1 │
│ │ nRF52840 │ [R1][C5] │
│ │ │ │
│ │ D0 D10│ [U1 TPS61220] │
│ │ D1 D9│ ●1 [L1][C1][C2] │
│ │ D2 D8│ │
│ │ D3 D7│ ┌────────────────┐ │
│ │ D4 3V3│ │ J1 FPC-20 0.5mm│ │
│ │ D5 GND│ └────────────────┘ │
│ │ D6 5V│ │
│ └───────────────┘ (M2) (M2) │
├ ─ ─ ─ ─ ─ SNAP ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ┤
│ ┌──────┐ ┃ ┌──────────┐ ┃ ┌──────────┐ │
│ │SOP-8 │ ┃ │SOP-16 N │ ┃ │SOP-16 W │ │
│ C│ │C┃C│ │C┃C│ │C │
│ A│[FPC] │A┃A│ [FPC] │A┃A│ [FPC] │A │
│ S│ │S┃S│ │S┃S│ │S │
│ T│ │T┃T│ │T┃T│ │T │
│ └──────┘ ┃ └──────────┘ ┃ └──────────┘ │
└───────────┸──────────────┸─────────────────────┘
C=castellated edges ┃=v-score snap lines
Each SOP adapter:
- Long edges (top/bottom): castellated half-holes = SOP pads
- Short edges: v-score snap lines
- Center top: FPC 0.5mm connector (20-pin for SOP-16, 10-pin for SOP-8)
- All SOP pins netted to corresponding FPC pins
"""
import uuid, os, json
def uid():
return str(uuid.uuid4())
# ============================================================
# KiCad drawing primitives
# ============================================================
def gr_line(x1, y1, x2, y2, layer="Edge.Cuts", w=0.1):
return f' (gr_line (start {x1:.3f} {y1:.3f}) (end {x2:.3f} {y2:.3f}) (layer "{layer}") (width {w}) (uuid "{uid()}"))'
def gr_rect(x1, y1, x2, y2, layer="F.SilkS", w=0.15):
return f' (gr_rect (start {x1:.3f} {y1:.3f}) (end {x2:.3f} {y2:.3f}) (layer "{layer}") (width {w}) (uuid "{uid()}"))'
def gr_text(s, x, y, sz=0.8, layer="F.SilkS", mirror=False):
th = max(0.08, sz * 0.13)
mir = " (justify mirror)" if mirror else ""
return f' (gr_text "{s}" (at {x:.3f} {y:.3f}) (layer "{layer}") (uuid "{uid()}") (effects (font (size {sz} {sz}) (thickness {th:.3f})){mir}))'
def gr_circle(x, y, r=0.3, layer="F.SilkS", fill="solid"):
return f' (gr_circle (center {x:.3f} {y:.3f}) (end {x+r:.3f} {y:.3f}) (layer "{layer}") (width 0.1) (fill {fill}) (uuid "{uid()}"))'
def fp_hdr(name, x, y, layer="F.Cu"):
return f"""
(footprint "panel:{name}" (layer "{layer}")
(at {x:.3f} {y:.3f})
(uuid "{uid()}")
(fp_text reference "{name}" (at 0 0) (layer "{layer[0]}.Fab") (uuid "{uid()}")
(effects (font (size 0.5 0.5) (thickness 0.08)) hide))
(fp_text value "" (at 0 0) (layer "{layer[0]}.Fab") (uuid "{uid()}")
(effects (font (size 0.5 0.5) (thickness 0.08)) hide))"""
def pad_smd(name, x, y, w, h, net, nname, layer="F.Cu"):
layers = f'"{layer}" "{layer[0]}.Paste" "{layer[0]}.Mask"'
return f' (pad "{name}" smd rect (at {x:.3f} {y:.3f}) (size {w:.3f} {h:.3f}) (layers {layers}) (net {net} "{nname}") (uuid "{uid()}"))'
def pad_thru(name, x, y, pd, dd, net, nname):
return f' (pad "{name}" thru_hole circle (at {x:.3f} {y:.3f}) (size {pd} {pd}) (drill {dd}) (layers "*.Cu" "*.Mask") (net {net} "{nname}") (uuid "{uid()}"))'
def pad_cast(name, x, y, net, nname):
"""Castellated half-hole on board edge."""
return f' (pad "{name}" thru_hole circle (at {x:.3f} {y:.3f}) (size 1.0 1.0) (drill 0.6) (layers "*.Cu" "*.Mask") (net {net} "{nname}") (uuid "{uid()}"))'
# ============================================================
# XIAO nRF52840 Dimensions (from Seeed docs)
# ============================================================
# PCB: 21.0mm x 17.5mm
# USB-C: centered on one 17.5mm short edge, ~9mm wide, protrudes ~2.5mm
# Pin headers: 2x7, 2.54mm pitch, rows 17.78mm apart (center-center)
# Pin 1 (D0) at top-left when USB faces left
# Reset button on USB side, LED on opposite side
XIAO_W = 21.0
XIAO_H = 17.5
XIAO_ROW_SPAN = 17.78 # center to center of pin rows
XIAO_USB_W = 8.9
XIAO_USB_H = 3.2
XIAO_USB_PROTRUDE = 1.5 # how far USB sticks past PCB edge
# ============================================================
# Main generator
# ============================================================
def generate():
# Panel dimensions
CARRIER_W = 44.0
CARRIER_H = 26.0
ADAPTER_STRIP_H = 14.0
PANEL_W = 48.0
PANEL_H = CARRIER_H + ADAPTER_STRIP_H + 1.0 # 1mm v-score gap
ox, oy = 100.0, 100.0 # KiCad origin
pcb = []
# ---- File header ----
pcb.append(f"""(kicad_pcb (version 20221018) (generator "panel_v4")
(general (thickness 1.6))
(paper "A4")
(title_block
(title "Baby Mobile Combined Panel v4")
(date "2026-03-11")
(rev "4.0")
(comment 1 "Carrier: XIAO nRF52840 + IS25LP128F + TPS61220 + FPC-20")
(comment 2 "Adapters: SOP-8, SOP-16N, SOP-16W — castellated, FPC connected")
(comment 3 "Order: JLCPCB, 2-layer, castellated holes=yes, v-score=yes")
)
(layers
(0 "F.Cu" signal) (31 "B.Cu" signal)
(34 "B.Paste" user) (35 "F.Paste" user)
(36 "B.SilkS" user "B.Silkscreen") (37 "F.SilkS" user "F.Silkscreen")
(38 "B.Mask" user "B.Mask") (39 "F.Mask" user "F.Mask")
(44 "Edge.Cuts" user)
(48 "B.Fab" user "B.Fab") (49 "F.Fab" user "F.Fab")
)
(setup
(pad_to_mask_clearance 0.05)
(pcbplotparams (layerselection 0x00010fc_ffffffff) (outputdirectory "gerbers/"))
)
(net 0 "")
(net 1 "GND") (net 2 "VBAT") (net 3 "3V3")
(net 4 "SPI_MOSI") (net 5 "SPI_MISO") (net 6 "SPI_SCK") (net 7 "FLASH_CS")
(net 8 "BOOST_SW") (net 9 "AUDIO_FILT")
""")
# 16 signal nets for SOP pins / FPC
for i in range(1, 17):
pcb.append(f' (net {i+9} "S{i}")')
# Total nets: 0-25
# ================================================================
# PANEL OUTLINE
# ================================================================
# Outer rectangle
pcb.append(gr_line(ox, oy, ox+PANEL_W, oy))
pcb.append(gr_line(ox+PANEL_W, oy, ox+PANEL_W, oy+PANEL_H))
pcb.append(gr_line(ox+PANEL_W, oy+PANEL_H, ox, oy+PANEL_H))
pcb.append(gr_line(ox, oy+PANEL_H, ox, oy))
# V-score: carrier / adapter strip
vs_y = oy + CARRIER_H + 0.5
pcb.append(gr_line(ox, vs_y, ox+PANEL_W, vs_y))
pcb.append(gr_text("▼ SNAP ▼", ox + PANEL_W/2, vs_y - 0.3, 0.5))
# V-score: between adapters
adapt_base = vs_y + 0.5
# SOP-8: 10mm wide, SOP-16N: 16mm wide, SOP-16W: 16mm wide
a8_w = 12.0
a16n_w = 16.0
a16w_w = 16.0
gap = 0.0 # v-score is zero-width
vs_x1 = ox + a8_w + 1.0
vs_x2 = vs_x1 + a16n_w
pcb.append(gr_line(vs_x1, adapt_base, vs_x1, oy + PANEL_H))
pcb.append(gr_line(vs_x2, adapt_base, vs_x2, oy + PANEL_H))
# ================================================================
# CARRIER: XIAO SOCKET with accurate outline
# ================================================================
# Place XIAO with USB-C facing left edge of carrier
xiao_cx = ox + 3 + XIAO_W/2 # center of XIAO
xiao_cy = oy + CARRIER_H/2
# Board outline rectangle
xb_l = xiao_cx - XIAO_W/2 # left edge of XIAO PCB
xb_r = xiao_cx + XIAO_W/2 # right edge
xb_t = xiao_cy - XIAO_H/2 # top
xb_b = xiao_cy + XIAO_H/2 # bottom
pcb.append(gr_rect(xb_l, xb_t, xb_r, xb_b, "F.SilkS", 0.2))
# USB-C rectangle protruding from left edge
usb_l = xb_l - XIAO_USB_PROTRUDE
usb_t = xiao_cy - XIAO_USB_W/2
usb_b = xiao_cy + XIAO_USB_W/2
pcb.append(gr_rect(usb_l, usb_t, xb_l, usb_b, "F.SilkS", 0.2))
# Fill USB area
pcb.append(gr_rect(usb_l + 0.3, usb_t + 0.3, xb_l - 0.1, usb_b - 0.3, "F.SilkS", 0.15))
pcb.append(gr_text("USB-C", usb_l + 2, xiao_cy, 0.5))
pcb.append(gr_text("XIAO nRF52840", xiao_cx + 1, xiao_cy, 0.8))
# Reset button indicator (top-left corner of XIAO near USB)
pcb.append(gr_text("RST", xb_l + 2, xb_t + 1.5, 0.4))
pcb.append(gr_circle(xb_l + 1, xb_t + 1.5, 0.5, "F.SilkS", "none"))
# Pin labels
left_labels = ["D0","D1","D2","D3","D4","D5","D6"]
right_labels = ["D10","D9","D8","D7","3V3","GND","5V"]
# Left row nets: SIG_1..7 → S1..S7 (from toy via FPC)
left_nets = [(10,"S1"),(11,"S2"),(12,"S3"),(13,"S4"),(14,"S5"),(15,"S6"),(16,"S7")]
# Right row: D10→S8(audio), D9→SCK, D8→MOSI, D7→MISO, 3V3, GND, 5V(NC)
right_nets = [(17,"S8"),(6,"SPI_SCK"),(4,"SPI_MOSI"),(5,"SPI_MISO"),(3,"3V3"),(1,"GND"),(0,"")]
# Left header
pcb.append(fp_hdr("J2_XIAO_L", xiao_cx - XIAO_ROW_SPAN/2, xiao_cy))
for i in range(7):
y = -7.62 + i * 2.54
net_id, net_name = left_nets[i]
pcb.append(pad_thru(left_labels[i], 0, y, 1.7, 1.0, net_id, net_name))
pcb.append(" )")
for i, lbl in enumerate(left_labels):
pcb.append(gr_text(lbl, xiao_cx - XIAO_ROW_SPAN/2 - 2.5, xiao_cy - 7.62 + i*2.54, 0.45))
# Right header
pcb.append(fp_hdr("J3_XIAO_R", xiao_cx + XIAO_ROW_SPAN/2, xiao_cy))
for i in range(7):
y = -7.62 + i * 2.54
net_id, net_name = right_nets[i]
if net_id > 0:
pcb.append(pad_thru(right_labels[i], 0, y, 1.7, 1.0, net_id, net_name))
else:
pcb.append(f' (pad "{right_labels[i]}" thru_hole circle (at 0 {y:.2f}) (size 1.7 1.7) (drill 1.0) (layers "*.Cu" "*.Mask") (uuid "{uid()}"))')
pcb.append(" )")
for i, lbl in enumerate(right_labels):
pcb.append(gr_text(lbl, xiao_cx + XIAO_ROW_SPAN/2 + 2.8, xiao_cy - 7.62 + i*2.54, 0.45))
# ================================================================
# CARRIER: IS25LP128F (SOIC-8)
# ================================================================
fl_cx = ox + 32
fl_cy = oy + 5.5
soic_span = 5.4
# SOIC-8 body outline on silk
pcb.append(gr_rect(fl_cx - 2.5, fl_cy - soic_span/2 - 0.5,
fl_cx + 2.5, fl_cy + soic_span/2 + 0.5))
# Pin 1 dot
pcb.append(gr_circle(fl_cx - 1.5, fl_cy + soic_span/2 - 0.5, 0.25))
# Notch on pin 1 end
pcb.append(gr_circle(fl_cx, fl_cy + soic_span/2 + 0.5, 0.4, "F.SilkS", "none"))
pcb.append(gr_text("U2", fl_cx, fl_cy - soic_span/2 - 1.5, 0.5))
pcb.append(gr_text("IS25LP128F", fl_cx, fl_cy + soic_span/2 + 2, 0.4))
# Pin numbers on silk
for i, num in enumerate([1,2,3,4]):
pcb.append(gr_text(str(num), fl_cx - 1.905 + i*1.27, fl_cy + soic_span/2 + 1.2, 0.3))
for i, num in enumerate([8,7,6,5]):
pcb.append(gr_text(str(num), fl_cx - 1.905 + i*1.27, fl_cy - soic_span/2 - 1.2, 0.3))
flash_pins = [
(1, -1.905, soic_span/2, 7, "FLASH_CS"),
(2, -0.635, soic_span/2, 5, "SPI_MISO"),
(3, 0.635, soic_span/2, 3, "3V3"), # ~WP tie high
(4, 1.905, soic_span/2, 1, "GND"),
(5, 1.905, -soic_span/2, 4, "SPI_MOSI"),
(6, 0.635, -soic_span/2, 6, "SPI_SCK"),
(7, -0.635, -soic_span/2, 3, "3V3"), # ~HOLD tie high
(8, -1.905, -soic_span/2, 3, "3V3"), # VCC
]
pcb.append(fp_hdr("U2_Flash", fl_cx, fl_cy))
for pin, x, y, net, nn in flash_pins:
pcb.append(pad_smd(str(pin), x, y, 0.6, 1.5, net, nn))
pcb.append(" )")
# Flash decoupling C3
pcb.append(fp_hdr("C3", fl_cx + 5.5, fl_cy - 1))
pcb.append(pad_smd("1", -1.0, 0, 1.0, 1.2, 3, "3V3"))
pcb.append(pad_smd("2", 1.0, 0, 1.0, 1.2, 1, "GND"))
pcb.append(" )")
pcb.append(gr_text("C3", fl_cx + 5.5, fl_cy - 2.3, 0.4))
pcb.append(gr_text("100n", fl_cx + 5.5, fl_cy + 0.3, 0.35))
# Flash CS pullup R2
pcb.append(fp_hdr("R2", fl_cx + 5.5, fl_cy + 2))
pcb.append(pad_smd("1", -1.0, 0, 1.0, 1.2, 7, "FLASH_CS"))
pcb.append(pad_smd("2", 1.0, 0, 1.0, 1.2, 3, "3V3"))
pcb.append(" )")
pcb.append(gr_text("R2", fl_cx + 5.5, fl_cy + 0.8, 0.4))
pcb.append(gr_text("10K", fl_cx + 5.5, fl_cy + 3.3, 0.35))
# ================================================================
# CARRIER: Audio RC filter (R1 + C5)
# ================================================================
rc_x = ox + 32
rc_y = oy + 14
pcb.append(fp_hdr("R1", rc_x, rc_y))
pcb.append(pad_smd("1", -1.0, 0, 1.0, 1.2, 17, "S8")) # from XIAO D10
pcb.append(pad_smd("2", 1.0, 0, 1.0, 1.2, 9, "AUDIO_FILT"))
pcb.append(" )")
pcb.append(gr_text("R1 4.7K", rc_x, rc_y - 1.3, 0.4))
pcb.append(fp_hdr("C5", rc_x, rc_y + 3))
pcb.append(pad_smd("1", -1.0, 0, 1.0, 1.2, 9, "AUDIO_FILT"))
pcb.append(pad_smd("2", 1.0, 0, 1.0, 1.2, 1, "GND"))
pcb.append(" )")
pcb.append(gr_text("C5 10n", rc_x, rc_y + 1.7, 0.4))
# ================================================================
# CARRIER: TPS61220 Boost Converter
# ================================================================
bx = ox + 32
by = oy + 21
# SC-70-5 outline
pcb.append(gr_rect(bx - 1.2, by - 1.1, bx + 1.2, by + 1.1))
pcb.append(gr_circle(bx - 0.8, by + 0.6, 0.2)) # pin 1 dot
pcb.append(gr_text("U1", bx, by - 2, 0.5))
pcb.append(gr_text("TPS61220", bx, by + 2, 0.4))
pcb.append(gr_text("●1", bx - 1.5, by + 0.7, 0.35))
pcb.append(fp_hdr("U1_Boost", bx, by))
pcb.append(pad_smd("1", -0.65, 0.7, 0.4, 0.55, 2, "VBAT")) # VIN
pcb.append(pad_smd("2", 0, 0.7, 0.4, 0.55, 1, "GND")) # GND
pcb.append(pad_smd("3", 0.65, 0.7, 0.4, 0.55, 2, "VBAT")) # EN=VIN
pcb.append(pad_smd("4", 0.65, -0.7, 0.4, 0.55, 3, "3V3")) # VOUT
pcb.append(pad_smd("5", -0.65, -0.7, 0.4, 0.55, 8, "BOOST_SW")) # L
pcb.append(" )")
# L1 (0805)
pcb.append(fp_hdr("L1", bx - 4, by))
pcb.append(pad_smd("1", -1.0, 0, 1.0, 1.2, 8, "BOOST_SW"))
pcb.append(pad_smd("2", 1.0, 0, 1.0, 1.2, 2, "VBAT"))
pcb.append(" )")
pcb.append(gr_text("L1 4.7u", bx - 4, by - 1.3, 0.4))
# C1 input (0805)
pcb.append(fp_hdr("C1", bx - 4, by + 3))
pcb.append(pad_smd("1", -1.0, 0, 1.0, 1.2, 2, "VBAT"))
pcb.append(pad_smd("2", 1.0, 0, 1.0, 1.2, 1, "GND"))
pcb.append(" )")
pcb.append(gr_text("C1 10u", bx - 4, by + 1.7, 0.4))
# C2 output (0805)
pcb.append(fp_hdr("C2", bx + 4, by))
pcb.append(pad_smd("1", -1.0, 0, 1.0, 1.2, 3, "3V3"))
pcb.append(pad_smd("2", 1.0, 0, 1.0, 1.2, 1, "GND"))
pcb.append(" )")
pcb.append(gr_text("C2 10u", bx + 4, by - 1.3, 0.4))
# ================================================================
# CARRIER: FPC-20 Connector (0.5mm pitch, bottom-contact)
# ================================================================
fpc_cx = ox + 38
fpc_cy = oy + 14
fpc_pitch = 0.5
n_fpc = 20
# FPC connector outline
fpc_w = (n_fpc - 1) * fpc_pitch + 2.0
pcb.append(gr_rect(fpc_cx - fpc_w/2, fpc_cy - 2, fpc_cx + fpc_w/2, fpc_cy + 2))
pcb.append(gr_text("J1 FPC-20", fpc_cx, fpc_cy - 3, 0.5))
pcb.append(gr_text("0.5mm TO TOY", fpc_cx, fpc_cy + 3, 0.35))
pcb.append(gr_circle(fpc_cx - (n_fpc-1)*fpc_pitch/2 - 0.8, fpc_cy, 0.2)) # pin 1
# FPC pin assignment:
# 1=VBAT 2=GND 3=S1 4=S2 ... 10=S8 11-16=S9-S14(spare) 17-20=spare/GND
fpc_nets = [
(1, 2, "VBAT"), (2, 1, "GND"),
(3, 10, "S1"), (4, 11, "S2"), (5, 12, "S3"), (6, 13, "S4"),
(7, 14, "S5"), (8, 15, "S6"), (9, 16, "S7"), (10, 17, "S8"),
(11, 18, "S9"), (12, 19, "S10"), (13, 20, "S11"), (14, 21, "S12"),
(15, 22, "S13"), (16, 23, "S14"), (17, 24, "S15"), (18, 25, "S16"),
(19, 1, "GND"), (20, 1, "GND"),
]
pcb.append(fp_hdr("J1_FPC20", fpc_cx, fpc_cy))
for pin, net, nn in fpc_nets:
x = -((n_fpc - 1) * fpc_pitch / 2) + (pin - 1) * fpc_pitch
pcb.append(pad_smd(str(pin), x, 0, 0.3, 1.2, net, nn))
# Anchor/lock pads
pcb.append(pad_smd("S1", -(fpc_w/2 - 0.5), 2.5, 1.5, 1.0, 0, ""))
pcb.append(pad_smd("S2", (fpc_w/2 - 0.5), 2.5, 1.5, 1.0, 0, ""))
pcb.append(" )")
# ================================================================
# CARRIER: Mounting holes
# ================================================================
for mx, my in [(ox + 2, oy + CARRIER_H - 2), (ox + CARRIER_W - 3, oy + CARRIER_H - 2)]:
pcb.append(fp_hdr("MH", mx, my))
pcb.append(f' (pad "" thru_hole circle (at 0 0) (size 3.5 3.5) (drill 2.2) (layers "*.Cu" "*.Mask") (uuid "{uid()}"))')
pcb.append(" )")
# Carrier back silk
pcb.append(gr_text("XIAO: D0-D6→SIG1-7 D7=MISO D8=MOSI D9=SCK D10=AUDIO(S8)", ox + CARRIER_W/2, oy + CARRIER_H/2, 0.4, "B.SilkS"))
pcb.append(gr_text("FPC: 1=VBAT 2=GND 3-10=S1-S8 19-20=GND", ox + CARRIER_W/2, oy + CARRIER_H/2 + 2, 0.4, "B.SilkS"))
# ================================================================
# ADAPTERS: Castellated SOP breakouts with FPC connectors
# ================================================================
SOP_PITCH = 1.27
def make_adapter(name, board_cx, board_cy, pins_per_side, row_span, n_fpc_pins):
"""
Adapter board with:
- Castellated half-holes on TOP and BOTTOM long edges (SOP pads)
- FPC connector centered on F.Cu
- Board edges through SOP pad centers
"""
total_pins = pins_per_side * 2
row_len = (pins_per_side - 1) * SOP_PITCH
bw = row_len + 3.0 # board width (along pin rows)
bh = row_span # board height = exactly SOP row spacing
# Board outline — edges at castellation centers
bl = board_cx - bw/2
br = board_cx + bw/2
bt = board_cy - bh/2 # top edge (pins N+1..2N)
bb = board_cy + bh/2 # bottom edge (pins 1..N)
# Don't draw left/right edges if they coincide with panel v-score
# (they'll be part of the panel outline or v-score already)
# Draw top and bottom edges
pcb.append(gr_line(bl, bt, br, bt))
pcb.append(gr_line(br, bt, br, bb))
pcb.append(gr_line(br, bb, bl, bb))
pcb.append(gr_line(bl, bb, bl, bt))
# Label
pcb.append(gr_text(name, board_cx, board_cy, 0.6))
# Castellated pads footprint
pcb.append(fp_hdr(f"{name}_cast", board_cx, board_cy, "B.Cu"))
for i in range(pins_per_side):
pin = i + 1
x = -row_len/2 + i * SOP_PITCH
net_id = pin + 9 # S1=net10, S2=net11, etc.
# Bottom edge: pins 1..N
pcb.append(pad_cast(str(pin), x, bh/2, net_id, f"S{pin}"))
# Top edge: pins 2N..N+1 (reversed, SOP convention)
top_pin = total_pins - i
top_net = top_pin + 9
pcb.append(pad_cast(str(top_pin), x, -bh/2, top_net, f"S{top_pin}"))
pcb.append(" )")
# Pin labels on front silk
for i in range(pins_per_side):
x = board_cx - row_len/2 + i * SOP_PITCH
pcb.append(gr_text(str(i+1), x, bb + 0.7, 0.3))
pcb.append(gr_text(str(total_pins - i), x, bt - 0.7, 0.3))
# Pin 1 dot
pcb.append(gr_circle(board_cx - row_len/2 - 0.5, bb + 0.5, 0.2))
pcb.append(gr_text("●1", board_cx - row_len/2 - 0.5, bb + 1.3, 0.3))
# Pin labels on back silk (mirror, for soldering reference)
pcb.append(gr_text(f"{name} ●1→", board_cx, board_cy, 0.5, "B.SilkS", mirror=True))
# FPC connector centered
fpc_pitch_a = 0.5
pcb.append(fp_hdr(f"{name}_FPC", board_cx, board_cy))
for j in range(n_fpc_pins):
x = -((n_fpc_pins - 1) * fpc_pitch_a / 2) + j * fpc_pitch_a
# Map FPC pins to SOP pin nets
if j < total_pins:
sop_pin = j + 1
net_id = sop_pin + 9
nn = f"S{sop_pin}"
elif j == n_fpc_pins - 2:
net_id = 1; nn = "GND" # second-to-last = GND
elif j == n_fpc_pins - 1:
net_id = 2; nn = "VBAT" # last = VBAT
else:
net_id = 0; nn = ""
pcb.append(pad_smd(f"F{j+1}", x, 0, 0.3, 1.0, net_id, nn))
# Anchor pads
aw = (n_fpc_pins - 1) * fpc_pitch_a / 2 + 1.5
pcb.append(pad_smd("SA", -aw, 1.5, 1.2, 0.8, 0, ""))
pcb.append(pad_smd("SB", aw, 1.5, 1.2, 0.8, 0, ""))
pcb.append(" )")
pcb.append(gr_text("FPC", board_cx, board_cy - 1.8, 0.35))
pcb.append(gr_circle(board_cx - (n_fpc_pins-1)*fpc_pitch_a/2 - 0.6, board_cy, 0.15))
# Place adapters in the strip
strip_cy = vs_y + 0.5 + ADAPTER_STRIP_H / 2
# SOP-8: 4+4 pins, 3.9mm span, 10-pin FPC (8 signals + GND + VBAT)
make_adapter("SOP-8", ox + a8_w/2 + 0.5, strip_cy, 4, 3.9, 10)
# SOP-16 narrow: 8+8 pins, 6.0mm span, 20-pin FPC (16 signals + GND + VBAT + 2 spare)
make_adapter("SOP-16N", vs_x1 + a16n_w/2, strip_cy, 8, 6.0, 20)
# SOP-16 wide: 8+8 pins, 10.3mm span, 20-pin FPC
make_adapter("SOP-16W", vs_x2 + a16w_w/2, strip_cy, 8, 10.3, 20)
# ================================================================
# Panel title
# ================================================================
pcb.append(gr_text("Baby Mobile v4 — JLCPCB Panel", ox + PANEL_W/2, oy - 2, 1.0))
pcb.append(gr_text("Castellated Holes=YES V-Score=YES 2-Layer 1.6mm", ox + PANEL_W/2, oy + PANEL_H + 2, 0.5))
pcb.append(")")
return "\n".join(pcb)
if __name__ == "__main__":
outdir = os.path.dirname(os.path.abspath(__file__))
pcb_text = generate()
pcb_path = os.path.join(outdir, "baby-mobile-panel.kicad_pcb")
with open(pcb_path, "w") as f:
f.write(pcb_text)
print(f"Written: {pcb_path} ({len(pcb_text)} bytes)")
proj = json.dumps({
"meta": {"filename": "baby-mobile-panel.kicad_pro", "version": 1},
"board": {"design_settings": {"rules": {"min_track_width": 0.15}}},
"net_settings": {"classes": [{"name":"Default","clearance":0.15,"track_width":0.25}]},
}, indent=2)
with open(os.path.join(outdir, "baby-mobile-panel.kicad_pro"), "w") as f:
f.write(proj)
print("\nPanel:")
print(" Carrier (44×26mm): XIAO(accurate outline+USB-C), IS25LP128F(pin1 dot+notch), TPS61220(pin1 dot), FPC-20")
print(" SOP-8 adapter: castellation on long edges, 10-pin FPC center")
print(" SOP-16N adapter: castellation on long edges, 20-pin FPC center")
print(" SOP-16W adapter: castellation on long edges, 20-pin FPC center")
print(" V-score between carrier and adapter strip, and between each adapter")
print(" All polarized parts have ●1 markers")
generate_v5.py
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#!/usr/bin/env python3
"""
Baby Mobile v5 — Integrated Schematic + PCB Generator
Fixes from v4 feedback:
(a) Generates BOTH .kicad_sch and .kicad_pcb
(b) XIAO USB-C on TOP edge, pin rows 15mm apart,
carrier pads extended to 20mm with castellated edges
(c) Each sub-board has unique net names:
- Carrier: C_S1..C_S8, C_VBAT, C_3V3, SPI_*, FLASH_CS, BOOST_SW, AUDIO_FILT
- SOP-8 adapter: A8_P1..A8_P8, A8_VBAT, A8_GND
- SOP-16N adapter: A16N_P1..A16N_P16, A16N_VBAT, A16N_GND
- SOP-16W adapter: A16W_P1..A16W_P16, A16W_VBAT, A16W_GND
FPC connects carrier nets to adapter nets (separate pins, separate nets)
(d) Key-shaped board: wide carrier head, narrow adapter stem
Adapters stacked vertically in stem, v-scored on narrow (short) edges
Board shape:
┌────────────────────────────┐
│ CARRIER (26×22mm) │
│ XIAO, Flash, Boost, │ wide "head"
│ FPC connector │
├──────┬─────────────┬───────┤
│ ADAPTER │ narrow "stem"
│ STRIP │
│ (12×30mm) │
│ SOP-8 │←v-score
│ SOP-16N │←v-score
│ SOP-16W │
└─────────────┘
"""
import uuid, os, json, sys
LIB = "bm"
def uid():
return str(uuid.uuid4())
# ============================================================
# NET DEFINITIONS — unique per sub-board
# ============================================================
# We'll build a flat net list. Each net gets a unique integer ID.
NETS = {}
_net_counter = [0]
def net(name):
"""Register a net name and return its ID."""
if name not in NETS:
_net_counter[0] += 1
NETS[name] = _net_counter[0]
return NETS[name]
def net_decl():
"""Generate all (net N "name") declarations."""
lines = [' (net 0 "")']
for name, idx in sorted(NETS.items(), key=lambda x: x[1]):
lines.append(f' (net {idx} "{name}")')
return "\n".join(lines)
# Pre-register all nets
# Carrier power
net("GND"); net("C_VBAT"); net("C_3V3"); net("BOOST_SW"); net("AUDIO_FILT")
# Carrier SPI (on-board, XIAO to flash)
net("SPI_MOSI"); net("SPI_MISO"); net("SPI_SCK"); net("FLASH_CS")
# Carrier signal nets (XIAO GPIOs that connect to FPC)
for i in range(1, 9):
net(f"C_S{i}")
# Carrier FPC pins (carrier side of cable)
for i in range(1, 21):
net(f"FPC_C{i}")
# SOP-8 adapter nets
for i in range(1, 9):
net(f"A8_P{i}")
net("A8_VBAT"); net("A8_GND")
for i in range(1, 11):
net(f"FPC_A8_{i}")
# SOP-16N adapter nets
for i in range(1, 17):
net(f"A16N_P{i}")
net("A16N_VBAT"); net("A16N_GND")
for i in range(1, 21):
net(f"FPC_A16N_{i}")
# SOP-16W adapter nets
for i in range(1, 17):
net(f"A16W_P{i}")
net("A16W_VBAT"); net("A16W_GND")
for i in range(1, 21):
net(f"FPC_A16W_{i}")
# ============================================================
# XIAO DIMENSIONS
# ============================================================
XIAO_PCB_W = 17.5 # board width (the short dimension when USB is up)
XIAO_PCB_H = 21.0 # board height (USB to antenna end)
XIAO_ROW_SPAN = 15.0 # center-to-center between pin rows
XIAO_USB_W = 8.9
XIAO_USB_H = 3.2
CARRIER_W = 26.0 # wide enough for 20mm pad span + margin
CARRIER_H = 24.0 # tall enough for XIAO + components below
CARRIER_PAD_SPAN = 20.0 # extended pad span for castellated hand soldering
STEM_W = 14.0 # narrow stem for adapters
SOP_PITCH = 1.27
FPC_PITCH = 0.5
# ============================================================
# KiCad primitives (same as before, abbreviated)
# ============================================================
def gl(x1,y1,x2,y2,layer="Edge.Cuts",w=0.1):
return f' (gr_line (start {x1:.3f} {y1:.3f}) (end {x2:.3f} {y2:.3f}) (layer "{layer}") (width {w}) (uuid "{uid()}"))'
def gr(x1,y1,x2,y2,layer="F.SilkS",w=0.15):
return f' (gr_rect (start {x1:.3f} {y1:.3f}) (end {x2:.3f} {y2:.3f}) (layer "{layer}") (width {w}) (uuid "{uid()}"))'
def gt(s,x,y,sz=0.8,layer="F.SilkS"):
th=max(0.08,sz*0.13)
return f' (gr_text "{s}" (at {x:.3f} {y:.3f}) (layer "{layer}") (uuid "{uid()}") (effects (font (size {sz} {sz}) (thickness {th:.3f}))))'
def gc(x,y,r=0.3,layer="F.SilkS"):
return f' (gr_circle (center {x:.3f} {y:.3f}) (end {x+r:.3f} {y:.3f}) (layer "{layer}") (width 0.1) (fill solid) (uuid "{uid()}"))'
def fp(name,x,y,layer="F.Cu"):
return f"""
(footprint "bm:{name}" (layer "{layer}")
(at {x:.3f} {y:.3f})
(uuid "{uid()}")
(fp_text reference "{name}" (at 0 0) (layer "{layer[0]}.Fab") (uuid "{uid()}")
(effects (font (size 0.5 0.5) (thickness 0.08)) hide))
(fp_text value "" (at 0 0) (layer "{layer[0]}.Fab") (uuid "{uid()}")
(effects (font (size 0.5 0.5) (thickness 0.08)) hide))"""
def ps(name,x,y,w,h,nid,nn,layer="F.Cu"):
ls=f'"{layer}" "{layer[0]}.Paste" "{layer[0]}.Mask"'
return f' (pad "{name}" smd rect (at {x:.3f} {y:.3f}) (size {w:.3f} {h:.3f}) (layers {ls}) (net {nid} "{nn}") (uuid "{uid()}"))'
def pt(name,x,y,pd,dd,nid,nn):
return f' (pad "{name}" thru_hole circle (at {x:.3f} {y:.3f}) (size {pd} {pd}) (drill {dd}) (layers "*.Cu" "*.Mask") (net {nid} "{nn}") (uuid "{uid()}"))'
def pc(name,x,y,nid,nn):
return f' (pad "{name}" thru_hole circle (at {x:.3f} {y:.3f}) (size 1.0 1.0) (drill 0.6) (layers "*.Cu" "*.Mask") (net {nid} "{nn}") (uuid "{uid()}"))'
# ============================================================
# PCB GENERATOR
# ============================================================
def generate_pcb():
ox, oy = 100.0, 100.0
# Adapter heights in the stem
a8_h = 8.0 # SOP-8 adapter board height (= row span 3.9mm + FPC tab)
a16n_h = 10.0 # SOP-16 narrow
a16w_h = 14.0 # SOP-16 wide (10.3mm span + FPC tab)
stem_h = a8_h + a16n_h + a16w_h
total_h = CARRIER_H + stem_h
pcb = []
pcb.append(f"""(kicad_pcb (version 20221018) (generator "bm_v5")
(general (thickness 1.6))
(paper "A4")
(title_block
(title "Baby Mobile v5 — Key-Shaped Panel")
(date "2026-03-11") (rev "5.0")
(comment 1 "Carrier head + breakaway adapter stem")
(comment 2 "Unique nets per sub-board, FPC interconnect")
)
(layers
(0 "F.Cu" signal) (31 "B.Cu" signal)
(34 "B.Paste" user) (35 "F.Paste" user)
(36 "B.SilkS" user "B.Silkscreen") (37 "F.SilkS" user "F.Silkscreen")
(38 "B.Mask" user "B.Mask") (39 "F.Mask" user "F.Mask")
(44 "Edge.Cuts" user)
(48 "B.Fab" user "B.Fab") (49 "F.Fab" user "F.Fab")
)
(setup (pad_to_mask_clearance 0.05)
(pcbplotparams (layerselection 0x00010fc_ffffffff) (outputdirectory "gerbers/")))
""")
# ---- KEY-SHAPED OUTLINE ----
# Carrier head: ox to ox+CARRIER_W, oy to oy+CARRIER_H
# Stem: centered under carrier, STEM_W wide
stem_l = ox + (CARRIER_W - STEM_W) / 2
stem_r = stem_l + STEM_W
stem_top = oy + CARRIER_H
stem_bot = stem_top + stem_h
# Clockwise outline
pcb.append(gl(ox, oy, ox+CARRIER_W, oy)) # top
pcb.append(gl(ox+CARRIER_W, oy, ox+CARRIER_W, stem_top)) # right carrier
pcb.append(gl(ox+CARRIER_W, stem_top, stem_r, stem_top)) # step right
pcb.append(gl(stem_r, stem_top, stem_r, stem_bot)) # right stem
pcb.append(gl(stem_r, stem_bot, stem_l, stem_bot)) # bottom stem
pcb.append(gl(stem_l, stem_bot, stem_l, stem_top)) # left stem
pcb.append(gl(stem_l, stem_top, ox, stem_top)) # step left
pcb.append(gl(ox, stem_top, ox, oy)) # left carrier
# V-score lines between adapters (horizontal, across stem width)
vs1_y = stem_top + a8_h
vs2_y = vs1_y + a16n_h
pcb.append(gl(stem_l, vs1_y, stem_r, vs1_y))
pcb.append(gl(stem_l, vs2_y, stem_r, vs2_y))
pcb.append(gt("SNAP", (stem_l+stem_r)/2, vs1_y-0.3, 0.4))
pcb.append(gt("SNAP", (stem_l+stem_r)/2, vs2_y-0.3, 0.4))
# ---- XIAO (USB on top edge, centered) ----
xiao_cx = ox + CARRIER_W / 2
xiao_top = oy + 1.5 # small margin from carrier top
xiao_bot = xiao_top + XIAO_PCB_H
# XIAO board outline
pcb.append(gr(xiao_cx - XIAO_PCB_W/2, xiao_top,
xiao_cx + XIAO_PCB_W/2, xiao_bot, "F.SilkS", 0.2))
# USB-C on top
pcb.append(gr(xiao_cx - XIAO_USB_W/2, xiao_top - XIAO_USB_H,
xiao_cx + XIAO_USB_W/2, xiao_top, "F.SilkS", 0.2))
pcb.append(gt("USB-C", xiao_cx, xiao_top - XIAO_USB_H/2, 0.45))
pcb.append(gt("XIAO nRF52840", xiao_cx, (xiao_top+xiao_bot)/2, 0.6))
pcb.append(gt("RST", xiao_cx - XIAO_PCB_W/2 + 2, xiao_top + 1.5, 0.35))
# Pin rows: 7 pins each, 2.54mm pitch, running vertically
# Left row at xiao_cx - 7.5mm, right row at xiao_cx + 7.5mm
# Pin 1 (D0) at top of left row
# Extended pads: each pad extends from 15mm span to carrier edge (20mm or board edge)
left_x = xiao_cx - XIAO_ROW_SPAN / 2
right_x = xiao_cx + XIAO_ROW_SPAN / 2
pin1_y = xiao_top + 3.0 # first pin position (some margin from USB)
left_pins = [
("D0", "C_S1"), ("D1", "C_S2"), ("D2", "C_S3"), ("D3", "C_S4"),
("D4", "C_S5"), ("D5", "C_S6"), ("D6", "C_S7"),
]
right_pins = [
("D10", "C_S8"), # audio PWM
("D9", "SPI_SCK"),
("D8", "SPI_MOSI"),
("D7", "SPI_MISO"),
("3V3", "C_3V3"),
("GND", "GND"),
("5V", ""), # not connected
]
# Left pin row with extended pads
pcb.append(fp("XIAO_L", left_x, pin1_y))
for i, (label, nn) in enumerate(left_pins):
y = i * 2.54
nid = net(nn) if nn else 0
# Through-hole at XIAO position
pcb.append(pt(label, 0, y, 1.7, 1.0, nid, nn))
# Extended SMD pad toward board left edge for castellated soldering
ext_x = -(CARRIER_PAD_SPAN/2 - XIAO_ROW_SPAN/2) # offset toward left edge
pcb.append(ps(f"{label}_ext", ext_x/2, y, abs(ext_x), 1.2, nid, nn))
pcb.append(" )")
# Right pin row with extended pads
pcb.append(fp("XIAO_R", right_x, pin1_y))
for i, (label, nn) in enumerate(right_pins):
y = i * 2.54
nid = net(nn) if nn else 0
if nid > 0:
pcb.append(pt(label, 0, y, 1.7, 1.0, nid, nn))
ext_x = (CARRIER_PAD_SPAN/2 - XIAO_ROW_SPAN/2)
pcb.append(ps(f"{label}_ext", ext_x/2, y, abs(ext_x), 1.2, nid, nn))
else:
pcb.append(f' (pad "{label}" thru_hole circle (at 0 {y:.2f}) (size 1.7 1.7) (drill 1.0) (layers "*.Cu" "*.Mask") (uuid "{uid()}"))')
pcb.append(" )")
# Pin labels
for i, (label, _) in enumerate(left_pins):
pcb.append(gt(label, left_x - 3.5, pin1_y + i*2.54, 0.4))
for i, (label, _) in enumerate(right_pins):
pcb.append(gt(label, right_x + 3.5, pin1_y + i*2.54, 0.4))
# ---- IS25LP128F (SOIC-8, below XIAO on carrier) ----
fl_cx = ox + 5
fl_cy = oy + CARRIER_H - 5
soic_span = 5.4
pcb.append(gr(fl_cx-2.5, fl_cy-soic_span/2-0.5, fl_cx+2.5, fl_cy+soic_span/2+0.5))
pcb.append(gc(fl_cx-1.5, fl_cy+soic_span/2-0.5, 0.25)) # pin 1
pcb.append(gt("U2 IS25LP128F", fl_cx, fl_cy-soic_span/2-1.5, 0.4))
pcb.append(gt("●1", fl_cx-2.2, fl_cy+soic_span/2+1, 0.3))
flash_pins = [
(1,-1.905, soic_span/2, "FLASH_CS"),
(2,-0.635, soic_span/2, "SPI_MISO"),
(3, 0.635, soic_span/2, "C_3V3"),
(4, 1.905, soic_span/2, "GND"),
(5, 1.905,-soic_span/2, "SPI_MOSI"),
(6, 0.635,-soic_span/2, "SPI_SCK"),
(7,-0.635,-soic_span/2, "C_3V3"),
(8,-1.905,-soic_span/2, "C_3V3"),
]
pcb.append(fp("U2", fl_cx, fl_cy))
for pin, x, y, nn in flash_pins:
pcb.append(ps(str(pin), x, y, 0.6, 1.5, net(nn), nn))
pcb.append(" )")
# C3 flash decoupling
pcb.append(fp("C3", fl_cx+5, fl_cy))
pcb.append(ps("1",-1.0,0, 1.0,1.2, net("C_3V3"),"C_3V3"))
pcb.append(ps("2", 1.0,0, 1.0,1.2, net("GND"),"GND"))
pcb.append(" )")
pcb.append(gt("C3 100n", fl_cx+5, fl_cy-1.3, 0.35))
# R2 CS pullup
pcb.append(fp("R2", fl_cx+5, fl_cy+3))
pcb.append(ps("1",-1.0,0, 1.0,1.2, net("FLASH_CS"),"FLASH_CS"))
pcb.append(ps("2", 1.0,0, 1.0,1.2, net("C_3V3"),"C_3V3"))
pcb.append(" )")
pcb.append(gt("R2 10K", fl_cx+5, fl_cy+1.7, 0.35))
# ---- TPS61220 + passives (bottom-right of carrier) ----
bx = ox + CARRIER_W - 6
by = oy + CARRIER_H - 5
pcb.append(gr(bx-1.2, by-1.1, bx+1.2, by+1.1))
pcb.append(gc(bx-0.8, by+0.6, 0.2))
pcb.append(gt("U1 TPS61220", bx, by-2.2, 0.4))
pcb.append(gt("●1", bx-1.5, by+0.7, 0.3))
pcb.append(fp("U1", bx, by))
pcb.append(ps("1",-0.65, 0.7, 0.4,0.55, net("C_VBAT"),"C_VBAT"))
pcb.append(ps("2", 0, 0.7, 0.4,0.55, net("GND"),"GND"))
pcb.append(ps("3", 0.65, 0.7, 0.4,0.55, net("C_VBAT"),"C_VBAT"))
pcb.append(ps("4", 0.65,-0.7, 0.4,0.55, net("C_3V3"),"C_3V3"))
pcb.append(ps("5",-0.65,-0.7, 0.4,0.55, net("BOOST_SW"),"BOOST_SW"))
pcb.append(" )")
pcb.append(fp("L1", bx-4, by))
pcb.append(ps("1",-1.0,0, 1.0,1.2, net("BOOST_SW"),"BOOST_SW"))
pcb.append(ps("2", 1.0,0, 1.0,1.2, net("C_VBAT"),"C_VBAT"))
pcb.append(" )")
pcb.append(gt("L1 4.7u", bx-4, by-1.3, 0.35))
pcb.append(fp("C1", bx-4, by+3))
pcb.append(ps("1",-1.0,0, 1.0,1.2, net("C_VBAT"),"C_VBAT"))
pcb.append(ps("2", 1.0,0, 1.0,1.2, net("GND"),"GND"))
pcb.append(" )")
pcb.append(gt("C1 10u", bx-4, by+1.7, 0.35))
pcb.append(fp("C2", bx+4, by))
pcb.append(ps("1",-1.0,0, 1.0,1.2, net("C_3V3"),"C_3V3"))
pcb.append(ps("2", 1.0,0, 1.0,1.2, net("GND"),"GND"))
pcb.append(" )")
pcb.append(gt("C2 10u", bx+4, by-1.3, 0.35))
# R1 + C5 audio filter
pcb.append(fp("R1", bx, by-6))
pcb.append(ps("1",-1.0,0, 1.0,1.2, net("C_S8"),"C_S8"))
pcb.append(ps("2", 1.0,0, 1.0,1.2, net("AUDIO_FILT"),"AUDIO_FILT"))
pcb.append(" )")
pcb.append(gt("R1 4.7K", bx, by-7.3, 0.35))
pcb.append(fp("C5", bx+4, by-6))
pcb.append(ps("1",-1.0,0, 1.0,1.2, net("AUDIO_FILT"),"AUDIO_FILT"))
pcb.append(ps("2", 1.0,0, 1.0,1.2, net("GND"),"GND"))
pcb.append(" )")
pcb.append(gt("C5 10n", bx+4, by-7.3, 0.35))
# ---- Carrier FPC-20 (at bottom of carrier, connecting to stem) ----
fpc_cx = ox + CARRIER_W / 2
fpc_cy = oy + CARRIER_H - 1.5
n_fpc = 20
pcb.append(gr(fpc_cx - n_fpc*FPC_PITCH/2 - 1, fpc_cy-1.5,
fpc_cx + n_fpc*FPC_PITCH/2 + 1, fpc_cy+1.5))
pcb.append(gt("J1 FPC-20 0.5mm", fpc_cx, fpc_cy-2.5, 0.4))
pcb.append(gc(fpc_cx - (n_fpc-1)*FPC_PITCH/2 - 0.6, fpc_cy, 0.15))
# FPC pin mapping: carrier side uses FPC_C1..FPC_C20
# 1=C_VBAT 2=GND 3-10=C_S1..C_S8 11-18=spare 19-20=GND
fpc_c_map = [
("FPC_C1","C_VBAT"), ("FPC_C2","GND"),
] + [(f"FPC_C{i+3}", f"C_S{i+1}") for i in range(8)] + [
(f"FPC_C{i}", "") for i in range(11,19)
] + [("FPC_C19","GND"), ("FPC_C20","GND")]
pcb.append(fp("J1_FPC", fpc_cx, fpc_cy))
for j in range(n_fpc):
x = -((n_fpc-1)*FPC_PITCH/2) + j*FPC_PITCH
nn = fpc_c_map[j][0]
nid = net(nn)
pcb.append(ps(str(j+1), x, 0, 0.3, 1.2, nid, nn))
pcb.append(ps("SA", -(n_fpc*FPC_PITCH/2+1), 2, 1.5, 1.0, 0, ""))
pcb.append(ps("SB", (n_fpc*FPC_PITCH/2+1), 2, 1.5, 1.0, 0, ""))
pcb.append(" )")
# ---- Mounting holes ----
for mx,my in [(ox+2, oy+2), (ox+CARRIER_W-2, oy+2)]:
pcb.append(fp("MH",mx,my))
pcb.append(f' (pad "" thru_hole circle (at 0 0) (size 3.5 3.5) (drill 2.2) (layers "*.Cu" "*.Mask") (uuid "{uid()}"))')
pcb.append(" )")
# ================================================================
# ADAPTER: SOP-8
# ================================================================
def make_adapter(prefix, center_x, top_y, height, pins_per_side, row_span, n_fpc_pins):
total_pins = pins_per_side * 2
row_len = (pins_per_side - 1) * SOP_PITCH
cy = top_y + height / 2
pcb.append(gt(prefix, center_x, cy, 0.5))
# Castellation pads on long (left/right) edges
# Bottom row: pins 1..N at cy + row_span/2
# Top row: pins 2N..N+1 at cy - row_span/2
pcb.append(fp(f"{prefix}_cast", center_x, cy, "B.Cu"))
for i in range(pins_per_side):
pin = i + 1
x = -row_len/2 + i * SOP_PITCH
nn = f"{prefix}_P{pin}"
pcb.append(pc(str(pin), x, row_span/2, net(nn), nn))
top_pin = total_pins - i
nn2 = f"{prefix}_P{top_pin}"
pcb.append(pc(str(top_pin), x, -row_span/2, net(nn2), nn2))
pcb.append(" )")
# Pin labels
for i in range(pins_per_side):
x = center_x - row_len/2 + i * SOP_PITCH
pcb.append(gt(str(i+1), x, cy + row_span/2 + 0.7, 0.3))
pcb.append(gt(str(total_pins-i), x, cy - row_span/2 - 0.7, 0.3))
pcb.append(gc(center_x - row_len/2 - 0.5, cy + row_span/2 + 0.5, 0.2))
# FPC connector centered
fpc_y = cy # centered vertically
pcb.append(fp(f"{prefix}_FPC", center_x, fpc_y))
for j in range(n_fpc_pins):
x = -((n_fpc_pins-1)*FPC_PITCH/2) + j*FPC_PITCH
if j < total_pins:
sop_pin = j + 1
nn = f"FPC_{prefix}_{j+1}"
elif j == n_fpc_pins - 2:
nn = f"{prefix}_GND"
elif j == n_fpc_pins - 1:
nn = f"{prefix}_VBAT"
else:
nn = f"FPC_{prefix}_{j+1}"
nid = net(nn)
pcb.append(ps(f"F{j+1}", x, 0, 0.3, 1.0, nid, nn))
pcb.append(ps("SA", -(n_fpc_pins*FPC_PITCH/2+1), 1.5, 1.2, 0.8, 0, ""))
pcb.append(ps("SB", (n_fpc_pins*FPC_PITCH/2+1), 1.5, 1.2, 0.8, 0, ""))
pcb.append(" )")
pcb.append(gt("FPC", center_x, fpc_y - 1.5, 0.3))
pcb.append(gc(center_x - (n_fpc_pins-1)*FPC_PITCH/2 - 0.5, fpc_y, 0.15))
stem_cx = (stem_l + stem_r) / 2
make_adapter("A8", stem_cx, stem_top, a8_h, 4, 3.9, 10)
make_adapter("A16N", stem_cx, vs1_y, a16n_h, 8, 6.0, 20)
make_adapter("A16W", stem_cx, vs2_y, a16w_h, 8, 10.3, 20)
# Back silk instructions
pcb.append(gt("Baby Mobile v5 — github.com/you/baby-mobile", ox+CARRIER_W/2, oy+CARRIER_H/2, 0.4, "B.SilkS"))
# ---- Insert net declarations at the top ----
# We need to do this after all nets are registered
net_block = net_decl()
pcb.insert(1, "") # placeholder, we'll join later
pcb.append(")")
# Splice net declarations in after the setup block
result = "\n".join(pcb)
result = result.replace("(setup (pad_to_mask_clearance 0.05)",
f"{net_block}\n\n (setup (pad_to_mask_clearance 0.05)")
return result
# ============================================================
# SCHEMATIC GENERATOR
# ============================================================
def generate_schematic():
"""Generate a matching .kicad_sch with all components and nets."""
sch = []
sch.append(f"""(kicad_sch (version 20230121) (generator "bm_v5_sch")
(uuid "{uid()}")
(paper "A3")
(title_block
(title "Baby Mobile v5 — Schematic")
(date "2026-03-11") (rev "5.0")
(comment 1 "XIAO nRF52840 + IS25LP128F + TPS61220")
(comment 2 "Key-shaped panel with breakaway SOP adapters")
)
""")
# Lib symbols (using the v2 fix: no library prefix on sub-symbols)
sch.append(" (lib_symbols")
# Generic 2-pin (for R, C, L)
for name, ref in [("R","R"), ("C","C"), ("L","L")]:
sch.append(f"""
(symbol "{LIB}:{name}" (in_bom yes) (on_board yes)
(property "Reference" "{ref}" (at 2 0 0) (effects (font (size 1.27 1.27))))
(property "Value" "{name}" (at 2 -2 0) (effects (font (size 1.27 1.27))))
(property "Footprint" "" (at 0 0 0) (effects (font (size 1.27 1.27)) hide))
(property "Datasheet" "" (at 0 0 0) (effects (font (size 1.27 1.27)) hide))
(symbol "{name}_0_1"
(rectangle (start -1 2.5) (end 1 -2.5) (stroke (width 0.254) (type default)) (fill (type background)))
)
(symbol "{name}_1_1"
(pin passive line (at 0 5 270) (length 2.5) (name "1" (effects (font (size 1 1)))) (number "1" (effects (font (size 1 1)))))
(pin passive line (at 0 -5 90) (length 2.5) (name "2" (effects (font (size 1 1)))) (number "2" (effects (font (size 1 1)))))
)
)""")
# TPS61220
sch.append(f"""
(symbol "{LIB}:TPS61220" (in_bom yes) (on_board yes)
(property "Reference" "U" (at 0 6 0) (effects (font (size 1.27 1.27))))
(property "Value" "TPS61220" (at 0 -6 0) (effects (font (size 1.27 1.27))))
(property "Footprint" "Package_TO_SOT_SMD:SOT-353_SC-70-5" (at 0 0 0) (effects (font (size 1.27 1.27)) hide))
(property "Datasheet" "" (at 0 0 0) (effects (font (size 1.27 1.27)) hide))
(symbol "TPS61220_0_1"
(rectangle (start -7 5) (end 7 -5) (stroke (width 0.254) (type default)) (fill (type background)))
)
(symbol "TPS61220_1_1"
(pin power_in line (at -10 3 0) (length 3) (name "VIN" (effects (font (size 1 1)))) (number "1" (effects (font (size 1 1)))))
(pin power_in line (at -10 -3 0) (length 3) (name "GND" (effects (font (size 1 1)))) (number "2" (effects (font (size 1 1)))))
(pin input line (at 10 -3 180) (length 3) (name "EN" (effects (font (size 1 1)))) (number "3" (effects (font (size 1 1)))))
(pin power_out line (at 10 3 180) (length 3) (name "VOUT" (effects (font (size 1 1)))) (number "4" (effects (font (size 1 1)))))
(pin passive line (at 0 8 270) (length 3) (name "L" (effects (font (size 1 1)))) (number "5" (effects (font (size 1 1)))))
)
)""")
# IS25LP128F
sch.append(f"""
(symbol "{LIB}:IS25LP128F" (in_bom yes) (on_board yes)
(property "Reference" "U" (at 0 9 0) (effects (font (size 1.27 1.27))))
(property "Value" "IS25LP128F" (at 0 7 0) (effects (font (size 1.27 1.27))))
(property "Footprint" "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" (at 0 0 0) (effects (font (size 1.27 1.27)) hide))
(property "Datasheet" "" (at 0 0 0) (effects (font (size 1.27 1.27)) hide))
(symbol "IS25LP128F_0_1"
(rectangle (start -7 6) (end 7 -6) (stroke (width 0.254) (type default)) (fill (type background)))
)
(symbol "IS25LP128F_1_1"
(pin input line (at -10 4 0) (length 3) (name "~{{CS}}" (effects (font (size 1 1)))) (number "1" (effects (font (size 1 1)))))
(pin output line (at -10 1.5 0) (length 3) (name "SO" (effects (font (size 1 1)))) (number "2" (effects (font (size 1 1)))))
(pin input line (at -10 -1.5 0) (length 3) (name "~{{WP}}" (effects (font (size 1 1)))) (number "3" (effects (font (size 1 1)))))
(pin power_in line (at -10 -4 0) (length 3) (name "GND" (effects (font (size 1 1)))) (number "4" (effects (font (size 1 1)))))
(pin input line (at 10 -4 180) (length 3) (name "SI" (effects (font (size 1 1)))) (number "5" (effects (font (size 1 1)))))
(pin input line (at 10 -1.5 180) (length 3) (name "SCLK" (effects (font (size 1 1)))) (number "6" (effects (font (size 1 1)))))
(pin input line (at 10 1.5 180) (length 3) (name "~{{HOLD}}" (effects (font (size 1 1)))) (number "7" (effects (font (size 1 1)))))
(pin power_in line (at 10 4 180) (length 3) (name "VCC" (effects (font (size 1 1)))) (number "8" (effects (font (size 1 1)))))
)
)""")
# FPC connector (generic N-pin)
for npins in [10, 20]:
sch.append(f"""
(symbol "{LIB}:FPC_{npins}" (in_bom yes) (on_board yes)
(property "Reference" "J" (at 0 {npins+2} 0) (effects (font (size 1.27 1.27))))
(property "Value" "FPC-{npins}" (at 0 {-npins-2} 0) (effects (font (size 1.27 1.27))))
(property "Footprint" "" (at 0 0 0) (effects (font (size 1.27 1.27)) hide))
(property "Datasheet" "" (at 0 0 0) (effects (font (size 1.27 1.27)) hide))
(symbol "FPC_{npins}_0_1"
(rectangle (start -3 {npins}) (end 3 {-npins}) (stroke (width 0.254) (type default)) (fill (type background)))
)
(symbol "FPC_{npins}_1_1"
""")
for i in range(npins):
y = npins - 1 - i * 2
sch.append(f' (pin passive line (at -6 {y} 0) (length 3) (name "P{i+1}" (effects (font (size 1 1)))) (number "{i+1}" (effects (font (size 1 1)))))')
sch.append(" )\n )")
# XIAO module symbol
sch.append(f"""
(symbol "{LIB}:XIAO_nRF52840" (in_bom yes) (on_board yes)
(property "Reference" "U" (at 0 22 0) (effects (font (size 1.27 1.27))))
(property "Value" "XIAO_nRF52840" (at 0 20 0) (effects (font (size 1.27 1.27))))
(property "Footprint" "" (at 0 0 0) (effects (font (size 1.27 1.27)) hide))
(property "Datasheet" "" (at 0 0 0) (effects (font (size 1.27 1.27)) hide))
(symbol "XIAO_nRF52840_0_1"
(rectangle (start -12 19) (end 12 -19) (stroke (width 0.254) (type default)) (fill (type background)))
)
(symbol "XIAO_nRF52840_1_1"
(pin bidirectional line (at -15 15 0) (length 3) (name "D0" (effects (font (size 1 1)))) (number "1" (effects (font (size 1 1)))))
(pin bidirectional line (at -15 12.5 0) (length 3) (name "D1" (effects (font (size 1 1)))) (number "2" (effects (font (size 1 1)))))
(pin bidirectional line (at -15 10 0) (length 3) (name "D2" (effects (font (size 1 1)))) (number "3" (effects (font (size 1 1)))))
(pin bidirectional line (at -15 7.5 0) (length 3) (name "D3" (effects (font (size 1 1)))) (number "4" (effects (font (size 1 1)))))
(pin bidirectional line (at -15 5 0) (length 3) (name "D4" (effects (font (size 1 1)))) (number "5" (effects (font (size 1 1)))))
(pin bidirectional line (at -15 2.5 0) (length 3) (name "D5" (effects (font (size 1 1)))) (number "6" (effects (font (size 1 1)))))
(pin bidirectional line (at -15 0 0) (length 3) (name "D6" (effects (font (size 1 1)))) (number "7" (effects (font (size 1 1)))))
(pin bidirectional line (at 15 15 180) (length 3) (name "D10" (effects (font (size 1 1)))) (number "8" (effects (font (size 1 1)))))
(pin bidirectional line (at 15 12.5 180) (length 3) (name "D9/SCK" (effects (font (size 1 1)))) (number "9" (effects (font (size 1 1)))))
(pin bidirectional line (at 15 10 180) (length 3) (name "D8/MOSI" (effects (font (size 1 1)))) (number "10" (effects (font (size 1 1)))))
(pin bidirectional line (at 15 7.5 180) (length 3) (name "D7/MISO" (effects (font (size 1 1)))) (number "11" (effects (font (size 1 1)))))
(pin power_in line (at 15 2.5 180) (length 3) (name "3V3" (effects (font (size 1 1)))) (number "12" (effects (font (size 1 1)))))
(pin power_in line (at 15 0 180) (length 3) (name "GND" (effects (font (size 1 1)))) (number "13" (effects (font (size 1 1)))))
(pin power_in line (at 15 -2.5 180) (length 3) (name "5V" (effects (font (size 1 1)))) (number "14" (effects (font (size 1 1)))))
)
)""")
sch.append(" )") # end lib_symbols
# Component instances (placed with net labels for connectivity)
def inst(lib_id, ref, value, footprint, x, y, angle=0):
return f""" (symbol (lib_id "{LIB}:{lib_id}") (at {x} {y} {angle}) (unit 1)
(in_bom yes) (on_board yes) (dnp no)
(uuid "{uid()}")
(property "Reference" "{ref}" (at {x+3} {y-3} 0) (effects (font (size 1.27 1.27))))
(property "Value" "{value}" (at {x+3} {y+3} 0) (effects (font (size 1.27 1.27))))
(property "Footprint" "{footprint}" (at {x} {y} 0) (effects (font (size 1.27 1.27)) hide))
(property "Datasheet" "" (at {x} {y} 0) (effects (font (size 1.27 1.27)) hide))
)"""
def label(name, x, y):
return f' (label "{name}" (at {x} {y} 0) (effects (font (size 1.27 1.27))) (uuid "{uid()}"))'
# Place components
sch.append(inst("XIAO_nRF52840", "U3", "XIAO_nRF52840", "", 80, 80))
sch.append(inst("IS25LP128F", "U2", "IS25LP128F", "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm", 180, 60))
sch.append(inst("TPS61220", "U1", "TPS61220", "Package_TO_SOT_SMD:SOT-353_SC-70-5", 180, 130))
sch.append(inst("FPC_20", "J1", "FPC-20 Carrier", "", 80, 160))
sch.append(inst("R", "R1", "4.7K", "Resistor_SMD:R_0805_2012Metric", 140, 80))
sch.append(inst("C", "C5", "10nF", "Capacitor_SMD:C_0805_2012Metric", 150, 90))
sch.append(inst("R", "R2", "10K", "Resistor_SMD:R_0805_2012Metric", 210, 50))
sch.append(inst("C", "C3", "100nF", "Capacitor_SMD:C_0805_2012Metric", 210, 70))
sch.append(inst("L", "L1", "4.7uH", "Inductor_SMD:L_0805_2012Metric", 180, 115))
sch.append(inst("C", "C1", "10uF", "Capacitor_SMD:C_0805_2012Metric", 160, 140))
sch.append(inst("C", "C2", "10uF", "Capacitor_SMD:C_0805_2012Metric", 200, 140))
# Adapter schematics (separate sections for clarity)
sch.append(inst("FPC_10", "J2", "FPC-10 SOP-8", "", 280, 80))
sch.append(inst("FPC_20", "J3", "FPC-20 SOP-16N", "", 280, 140))
sch.append(inst("FPC_20", "J4", "FPC-20 SOP-16W", "", 280, 200))
# Net labels (connecting everything logically)
# XIAO to SPI flash
labels = [
("SPI_SCK", 95, 67.5), ("SPI_SCK", 190, 58.5),
("SPI_MOSI", 95, 70), ("SPI_MOSI", 190, 56),
("SPI_MISO", 95, 72.5), ("SPI_MISO", 170, 61.5),
("FLASH_CS", 170, 64), ("FLASH_CS", 210, 45),
("C_3V3", 95, 77.5), ("C_3V3", 190, 64), ("C_3V3", 190, 133),
("GND", 95, 80), ("GND", 170, 56), ("GND", 170, 127),
# XIAO signals to carrier FPC
("C_S1", 65, 65), ("C_S2", 65, 67.5), ("C_S3", 65, 70),
("C_S4", 65, 72.5), ("C_S5", 65, 75), ("C_S6", 65, 77.5),
("C_S7", 65, 80), ("C_S8", 95, 65),
("C_S8", 130, 80), # to R1
("AUDIO_FILT", 150, 80),
# Boost
("C_VBAT", 170, 133), ("C_VBAT", 180, 110),
("BOOST_SW", 180, 122), ("BOOST_SW", 180, 120),
]
for name, x, y in labels:
sch.append(label(name, x, y))
# Text notes
notes = [
(40, 30, "CARRIER: XIAO nRF52840 + IS25LP128F (16MB) + TPS61220 (3.3V boost)"),
(40, 35, "FPC-20 cable connects carrier to one of the SOP adapter boards"),
(250, 30, "ADAPTERS: Snap-off castellated SOP footprints"),
(250, 35, "Each has its own FPC connector + unique net names"),
]
for x, y, text in notes:
sch.append(f' (text "{text}" (at {x} {y} 0) (effects (font (size 1.5 1.5)) (justify left)) (uuid "{uid()}"))')
sch.append(")")
return "\n".join(sch)
# ============================================================
# MAIN
# ============================================================
if __name__ == "__main__":
outdir = os.path.dirname(os.path.abspath(__file__))
# Generate PCB
pcb_text = generate_pcb()
pcb_path = os.path.join(outdir, "baby-mobile-v5.kicad_pcb")
with open(pcb_path, "w") as f:
f.write(pcb_text)
print(f"PCB: {pcb_path} ({len(pcb_text)} bytes)")
# Generate Schematic
sch_text = generate_schematic()
sch_path = os.path.join(outdir, "baby-mobile-v5.kicad_sch")
with open(sch_path, "w") as f:
f.write(sch_text)
print(f"SCH: {sch_path} ({len(sch_text)} bytes)")
# Generate Project
proj = json.dumps({
"meta": {"filename": "baby-mobile-v5.kicad_pro", "version": 1},
"board": {"design_settings": {"rules": {"min_track_width": 0.15, "min_via_diameter": 0.4}}},
"net_settings": {"classes": [
{"name": "Default", "clearance": 0.15, "track_width": 0.25},
{"name": "Power", "clearance": 0.2, "track_width": 0.5},
]},
}, indent=2)
with open(os.path.join(outdir, "baby-mobile-v5.kicad_pro"), "w") as f:
f.write(proj)
print(f"\n{len(NETS)} unique nets registered:")
print(f" Carrier: C_S1-8, C_VBAT, C_3V3, SPI_*, FLASH_CS, BOOST_SW, AUDIO_FILT")
print(f" SOP-8: A8_P1-8, A8_VBAT, A8_GND, FPC_A8_1-10")
print(f" SOP-16N: A16N_P1-16, A16N_VBAT, A16N_GND, FPC_A16N_1-20")
print(f" SOP-16W: A16W_P1-16, A16W_VBAT, A16W_GND, FPC_A16W_1-20")
print(f" No shared nets between carrier and adapters (FPC bridges them)")
print(f"\nKey-shaped board:")
print(f" Head (carrier): {CARRIER_W}×{CARRIER_H}mm")
print(f" Stem (adapters): {STEM_W}mm wide, stacked SOP-8 + SOP-16N + SOP-16W")
print(f" XIAO: USB-C on top, rows {XIAO_ROW_SPAN}mm apart, pads extended to {CARRIER_PAD_SPAN}mm")